Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2347

29

0b

RWC

This bit is set when USB2, as a master, 

receives a master-abort status on a memory access. This is treated as a Host Error and 

halts the DMA engines. This event can optionally generate an SERR# by setting the 

SERR# Enable bit and the SERR on Aborts Enable (bit 3, offset 84h). Software clears 

this bit by writing a '1' to this bit location.

Core

28

0b

RWC

This bit is set when USB2, as a master, 

receives a target abort status on a memory access. This is treated as a Host Error and 

halts the DMA engines. This event can optionally generate an SERR# by setting the 

SERR# Enable bit and the SERR on Aborts Enable (bit 3, offset 84h). Software clears 

this bit by writing a '1' to this bit location.

Core

27

0b

RO

This bit is used to indicate when the USB2 

function responds to a cycle with a target abort. There is no reason for this to happen, 

so this bit will be hard-wired to '0'. Read-Only

Core

26:25

01b

RO

This 2-bit field defines the timing for DEVSEL# 

assertion. Read-Only.

Core

24

0b

RWC

This bit is set whenever a data 

parity error is detected on a USB2 read completion packet on the internal interface to 

the USB2 host controller and bit 6 of the Command register is set to 1. Software clears 

this bit by writing a '1' to this bit location.

Core

23

1b

RO

Reserved as '1'.

Core

22

0b

RO

Reserved as '0'

Core

21

0b

RO

Reserved as '0'

Core

20

1b

RO

Hardwired to '1' indicating that offset 34h contains a 

valid capabilities pointer.

Core

19

0b

RO

This read-only bit reflects the state of this function's 

interrupt at the input of the enable/disable logic. This bit is a 1 when the interrupt is 

asserted. This bit will be 0 when the interrupt is deasserted. The value reported in this 

bit is independent of the value in the Interrupt Enable bit.

Core

18:11

00000000b

RO

Reserved.