Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2348

Datasheet

10

0b

RW

When cleared to '0', the function is capable of 

generating interrupts. When '1', the function can not generate its interrupt to the 

interrupt controller. Note that the corresponding Interrupt Status bit is not affected by 

the interrupt enable. This bit defaults to '0'. This bit is added as part of the PCI 2.3 

Specification.

Core

9

0b

RO

Reserved as '0'.

Core

8

0b

RW

on a memory read completion (if SERR on Aborts Enable 

is also set) Detection of an address or command parity error and the Parity Error 

Response bit is setDetection of a data parity error (when the data is going to the EHC) 

and the Parity Error Response bit is set

Core

7

0b

RO

Reserved as '0'.

Core

6

0b

RW

When set to 1, the USB2 Host Controller will check 

for correct parity (on its internal interface) and halt operation when bad parity is 

detected during the data phase as recommended by the EHCI specification. If it detects 

bad parity on the address or command phases when this bit is set to 1, the host 

controller does not take the cycle, halts the host controller (if currently not halted) and 

sets the host system error bit in the USBSTS register. Note that this applies to both 

requests and completions from the system interface. See section 9.19.2.4 for 

information regarding parity errors detected by the Prefetch DMA Engine. This bit must 

be set in order for the parity errors to generate SERR#.

Core

5

0b

RO

Reserved as '0'

Core

4

0b

RO

Reserved as '0'

Core

3

0b

RO

Reserved as '0'

Core

2

0b

RW

When set, bus mastering from EHCI is allowed, and will 

generate memory reads and writes for USB transfers. Notes on the EHC 

implementation: - Writes to change this bit occur immediately. Specifically, a write 

followed by a read will return the updated value. - When the BME bit is changed from 1 

to 0, the EHC will cease accessing main memory within 2 microframes (250 usec). 

During this time, any number of reads and/or writes to memory may occur. - Clearing 

the BME bit shuts down the EHC DMA engines in the same manner that clearing the 

Run/Stop does. However, the schedule status bits and the HCHalted bit do not change 

based on the BME value.

Core

1

0b

RW

This bit controls access to the USB2 Memory Space 

registers. If this bit is set, accesses to the USB2 registers are enabled. The Base 

Address register for USB2 should be programmed before this bit is set.

Core