Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2476
Datasheet
19.6.11
PAGESIZE—Offset 28h
Page Size Register Bit Definitions. This register is used by software to enable or disable
the reporting of the reception of specific USB Device Notification Transaction Packets. A
Notification Enable (Nx, where x = 0 to 15) flag is defined for each of the 16 possible
device notification types. If a flag is set for a specific notification type, a Device
Notification Event shall be generated when the respective notification packet is
received. After reset all notifications are disabled. Refer to section 6.4.2.7. This register
shall be written as a Dword. Byte writes produce undefined results.
Access Method
Default: 00000001h
19.6.12
DNCTRL—Offset 34h
Device Notification Register Bit Definitions.
Access Method
7:5
0h
RO
RSVD10:
reserved
4
0h
RW
PCD:
Reserved.
3
0h
RO
EINT:
Reserved.
2
0h
RO
HSE:
Reg field HSE
1
0h
RO
RSVD9:
reserved
0
1h
RO
HCH:
Reg field HCH
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
PAGESIZE:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RSV
D
12
PA
G
E
_
S
IZ
E
Bit
Range
Default &
Access
Description
31:16
0h
RO
RSVD12:
reserved
15:0
1h
RO
PAGE_SIZE:
Reg field PAGE_SIZE