Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2475

USB Command Register Bit Definitions

Default: 00000001h

0

0h

RW

Run/Stop (R/S) RW. Default = 0. 1 = Run. 0 = Stop. When set to a 1, the xHC 

proceeds with execution of the schedule. The xHC continues execution as long as this bit 

is set to a 1. When this bit is cleared to 0, the xHC completes any current or queued 

commands or TDs, and any USB transactions associated with them, then halts. Refer to 

section 5.4.1.1 for more information on how R/S shall be managed. The xHC shall halt 

within 16 ms. after software clears the Run/Stop bit if the above conditions have been 

met. The HCHalted (HCH) bit in the USBSTS register indicates when the xHC has 

finished its pending pipelined transactions and has entered the stopped state. Software 

shall not write a 1 to this flag unless the xHC is in the Halted state (i.e. HCH in the 

USBSTS register is 1). Doing so may yield undefined results. Writing a 0 to this flag 

when the xHC is in the Running state (i.e. HCH = 0) and any Event Rings are in the 

Event Ring Full state (refer to section 4.9.4) may result in lost events. When this 

register is exposed by a Virtual Function (VF), this bit only controls the run state of the 

xHC instance presented by the selected VF. Refer to section 8 for more information.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

RSVD

11

HC

E

CN

R

SRE

RS

S

SS

S

RSVD

10

PC

D

EINT

HS

E

RSVD9

HC

H

31:13

0h

RO

reserved

12

0h

RO

Host Controller Error (HCE) - RO. Default = 0. 0' = No internal xHC error 

conditions exist '1' = Internal xHC error condition. This flag shall be set to indicate that 

an internal error condition has been detected which requires software to reset and 

reinitialize the xHC. Refer to section 4.24.1 of xhci specification for more information.

11

0h

RO

Controller Not Ready (CNR) - RO. Default = '1'. '0' = Ready '1' = Not Ready. 

Software shall not write any Doorbell or Operational register of the xHC, other than the 

USBSTS register, until CNR = '0'. This flag is set by the xHC after a Chip Hardware Reset 

and cleared when the xHC is ready to begin accepting register writes. This flag shall 

remain cleared ('0') until the next Chip Hardware Reset.

10

0h

RO

Save/Restore Error (SRE) -RW1C. Default = '0'. If an error occurs during a Save or 

Restore operation this bit shall be set to '1'. This bit shall be cleared to '0' when a Save 

or Restore operation is initiated or when written with '1'. Refer to section 4.23.2 of xhci 

specification for more information.

9

0h

RO

Restore State Status: This bit is similar to the USBSTS.RSS in host mode. When 

the controller has finished the save process, it will complete the command by setting 

DSTS.RSS to '0'.

8

0h

RO

Save State Status: This bit is similar to the USBSTS.SSS in host mode. When the 

controller has finished the save process, it will complete the command by setting 

DSTS.SSS to '0'