Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2707
20.6.8
WAKESTS—Offset Eh
Wake Status
Access Method
Default: 00h
20.6.9
GSTS—Offset 10h
Global Status
Access Method
Default: 0000h
Type:
Memory Mapped I/O Register
(Size: 8 bits)
WAKESTS:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
RESE
RVED
0
SD
IN_S
TA
TE
Bit
Range
Default &
Access
Description
7:4
0h
RO
RESERVED0:
reserved
3:0
0h
RO
SDIN_STATE:
Flag bits that indicate which SDI signal s received a State Change event.
The bits are cleared by writing 1 s to them.
Type:
Memory Mapped I/O Register
(Size: 16 bits)
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RE
SE
RVED
0
FLUS
H_
ST
A
T
US
RE
SE
RVED
1
Bit
Range
Default &
Access
Description
15:2
0000h
RO
RESERVED0:
reserved
1
0h
RW
FLUSH_STATUS:
This bit is set to a 1 by the hardware to indicate that the flush cycle
initiated when the FCNTRL bit was set has completed. Software must write a 1to clear
this bit before the next time FCNTRL is set.