Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
System Memory Controller
Intel
®
Atom™ Processor E3800 Product Family
278
Datasheet
12.2
Features
The system memory controller supports the following DDR3L DRAM technologies, Data
Transfer Rates, SO-DIMM Modules and other features:
Transfer Rates, SO-DIMM Modules and other features:
•
DDR3L Data Transfer Rates (Fixed per SKU): 1066MT/s (Theoretical Maximum
Bandwidth: 8.5 GB/s per channel) or 1333MT/s (Theoretical Maximum Bandwidth:
10.6 GB/s per channel)
Bandwidth: 8.5 GB/s per channel) or 1333MT/s (Theoretical Maximum Bandwidth:
10.6 GB/s per channel)
•
DDR3L SDRAM’s (1.35 V DRAM interface I/Os, including DDR3L-RS)
•
DDR3L DRAM Device Technology
Table 151. ECC Signals and Memory Channel 1 Signal Muxing
Memory Channel 1 Signal Names
Ball #
Signal Names when ECC is
Enabled
DRAM1_DQ[56]
AM52
DRAM0_ECC_DQ[0]
DRAM1_DQ[57]
AL51
DRAM0_ECC_DQ[1]
DRAM1_DQ[58]
AG53
DRAM0_ECC_DQ[2]
DRAM1_DQ[59]
AG51
DRAM0_ECC_DQ[3]
DRAM1_DQ[60]
AL53
DRAM0_ECC_DQ[4]
DRAM1_DQ[61]
AK51
DRAM0_ECC_DQ[5]
DRAM1_DQ[62]
AF52
DRAM0_ECC_DQ[6]
DRAM1_DQ[63]
AF51
DRAM0_ECC_DQ[7]
DRAM1_DM[7]
AK52
DRAM0_ECC_DM
DRAM1_DQSP[7]
AH52
DRAM0_ECC_DQSP
DRAM1_DQSN[7]
AJ51
DRAM0_ECC_DQSN
Table 152. ECC Signals
Signal Name
Direction
Type
Description
DRAM0_ECC_DQ[7:0]
I/O
DDR3
ECC Check Data Bits
These are muxed with channel 1.
These are muxed with channel 1.
DRAM0_ECC_DM
O
DDR3
ECC Data Mask: DM is an optional output mask signal
for write data. Output data is masked when DM is
sampled HIGH coincident with that output data during a
Write access. DM is sampled on both edges of ECC_DQS.
This signal is muxed with channel 1 and may not be
needed.
for write data. Output data is masked when DM is
sampled HIGH coincident with that output data during a
Write access. DM is sampled on both edges of ECC_DQS.
This signal is muxed with channel 1 and may not be
needed.
DRAM0_ECC_DQSP
DRAM0_ECC_DQSN
I/O
DDR3
ECC Data Strobes: The data is captured at the crossing
point the ‘P’ and its compliment ‘N’ during read and write
transactions. For reads, the strobe crossover and data
are edge aligned, whereas in the Write command, the
strobe crossing is in the centre of the data window.
These are muxed with channel 1.
point the ‘P’ and its compliment ‘N’ during read and write
transactions. For reads, the strobe crossover and data
are edge aligned, whereas in the Write command, the
strobe crossing is in the centre of the data window.
These are muxed with channel 1.