Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
System Memory Controller
Intel
®
Atom™ Processor E3800 Product Family
280
Datasheet
The frequency of system memory is fixed based on SKU. Timing parameters (CAS
latency or CL + AL for DDR3, tRAS, tRCD, tRP) must be programmed to match within a
channel (Contact your Intel field representative for more information on memory
reference code (MRC)). The controller supports these configurations:
latency or CL + AL for DDR3, tRAS, tRCD, tRP) must be programmed to match within a
channel (Contact your Intel field representative for more information on memory
reference code (MRC)). The controller supports these configurations:
— Supports 1 SO-DIMM per channel.
— Each SO-DIMM can have 1 or 2 ranks.
— If a SO-DIMM has two ranks, then both ranks must be symmetrical (same chip
width, same chip density, and same total memory size per rank).
— For dual channel population, the two channels must be populated symmetrically
(chip width, density, ranks).
— The maximum total memory supported by the SoC is 8GB. Contact your Intel
representative for guidelines on the specific SO-DIMM Raw cards supported.
12.2.2
Rules for Populating SO-DIMM Slots
SO-DIMMs must share DRAM technology and total capacity. When channel 0 is
populated with a SO-DIMM, the other channel must either be identical (same DRAM
density, width, and number of ranks) or empty.
populated with a SO-DIMM, the other channel must either be identical (same DRAM
density, width, and number of ranks) or empty.
§
Table 155. Supported DDR3L SO-DIMM Size
DRAM
Chip
Density
Module
Size
# of chips
needed
DRAM
Chip Data
Width
Data Bus
Width
# of Ranks
needed
# of chips
/rank
1Gbit
2GB
16
x8
x64
2
8
2Gbit
1GB
4
x16
x64
1
4
2Gbit
2GB
8 (9 w/ECC)
x8
x64
1
8
2Gbit
4GB
16 (18 w/ECC)
x8
x64
2
8
4Gbit
4GB
8
x8
x64
1
8
4Gbit
8GB
16 (18 w/ECC)
x8
x64
2
8