Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
2810
Datasheet
in multiples of 1, 2 or 4 bytes, depending upon the EDSS value, and must also transfer
one FIFO entry per access. When the SSCR0.EDSS bit is set, DMA bursts must be in
multiples of 4 bytes (the DMA must have the Enhanced SSP configured as a 32-bit
peripheral).The DMA’s width register must be at least the SSP data size programmed
into the SSP control registers EDSS and DSS. The FIFO is seen as one 32-bit location by
the processor. For Writes, the Enhanced SSP port takes the data from the Transmit
FIFO, serializes it, and sends it over the serial wire (I2S[2:0]_DATAOUT) to the external
peripheral. Receive data from the external peripheral (on I2S[2:0]_DATAIN) is
converted to parallel words and stored in the Receive FIFO.
one FIFO entry per access. When the SSCR0.EDSS bit is set, DMA bursts must be in
multiples of 4 bytes (the DMA must have the Enhanced SSP configured as a 32-bit
peripheral).The DMA’s width register must be at least the SSP data size programmed
into the SSP control registers EDSS and DSS. The FIFO is seen as one 32-bit location by
the processor. For Writes, the Enhanced SSP port takes the data from the Transmit
FIFO, serializes it, and sends it over the serial wire (I2S[2:0]_DATAOUT) to the external
peripheral. Receive data from the external peripheral (on I2S[2:0]_DATAIN) is
converted to parallel words and stored in the Receive FIFO.
A programmable FIFO trigger threshold, when exceeded, generates an Interrupt or
DMA service request that, if enabled, signals the CPU or DMA respectively to empty the
Receive FIFO or to refill the Transmit FIFO.
DMA service request that, if enabled, signals the CPU or DMA respectively to empty the
Receive FIFO or to refill the Transmit FIFO.
The Transmit and Receive FIFOs are differentiated by whether the access is a Read or a
Write transfer. Reads automatically target the Receive FIFO, while Writes will write data
to the Transmit FIFO. From a memory-map perspective, they are at the same address.
FIFOs are 16 samples deep by 32 bits wide. Each read or write is to 1 SSP sample.
Write transfer. Reads automatically target the Receive FIFO, while Writes will write data
to the Transmit FIFO. From a memory-map perspective, they are at the same address.
FIFOs are 16 samples deep by 32 bits wide. Each read or write is to 1 SSP sample.
21.6.5
Supported Formats
The SSP consists of four pins that are used to transfer data between the SoC and
external Audio codecs, modems, or other peripherals. Although four serial-data formats
exist, each has the same basic structure, and in all cases the following pins are used in
the following manner:
external Audio codecs, modems, or other peripherals. Although four serial-data formats
exist, each has the same basic structure, and in all cases the following pins are used in
the following manner:
•
I2Sx_CLK—Defines the bit rate at which serial data is driven onto and sampled
from the port
from the port
•
I2Sx_FRM—Defines the boundaries of a basic data “unit,” comprised of multiple
serial bits
serial bits
•
I2Sx_DATAIN—The serial data path for transmitted data, from system to peripheral
•
I2Sx_DATAOUT—The serial data path for received data, from peripheral to system
A data frame can contain from 4 to 32 bits, depending on the selected format. Serial
data is transmitted most significant bit first. The Programmable Serial Protocol (PSP)
format is used to implement I
data is transmitted most significant bit first. The Programmable Serial Protocol (PSP)
format is used to implement I
2
S.
Master and Slave modes are supported. When driven by the Enhanced SSP, the
I2Sx_CLK only toggles during active transfers (not continuously) unless ECRA/ECRB
functions are used. When the I2Sx_CLK is driven by another device, it is allowed to be
either continuous or only driven during transfers, but certain restrictions on PSP
parameters apply.
I2Sx_CLK only toggles during active transfers (not continuously) unless ECRA/ECRB
functions are used. When the I2Sx_CLK is driven by another device, it is allowed to be
either continuous or only driven during transfers, but certain restrictions on PSP
parameters apply.
Normally, the serial clock (I2Sx_CLK), if driven by the Enhanced SSP Port, only toggles
while an active data transfer is underway. There are several conditions, however, that
may cause the clock to run continuously. If the Receive With Out Transmit mode is
enabled by setting the SSCR1.RWOT bit to 1, the I2Sx_CLK will toggle regardless of
whether Transmit data exists within the Transmit FIFO. The I2Sx_CLK will also toggle
while an active data transfer is underway. There are several conditions, however, that
may cause the clock to run continuously. If the Receive With Out Transmit mode is
enabled by setting the SSCR1.RWOT bit to 1, the I2Sx_CLK will toggle regardless of
whether Transmit data exists within the Transmit FIFO. The I2Sx_CLK will also toggle