Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2811
continuously if the Enhanced SSP is in Network mode, or if ECRA, or ECRB is enabled.
At other times, I2Sx_CLK will be held in an inactiveI2Sx_FRM or idle state, as defined
by the specified protocol under which it operates.
At other times, I2Sx_CLK will be held in an inactiveI2Sx_FRM or idle state, as defined
by the specified protocol under which it operates.
21.6.5.1
Programmable Serial Protocol (PSP)
There are many variations of the frame behavior for different codecs and protocol
formats. To allow flexibility the PSP format allows I2Sx_FRM to be programmable in
direction, delay, polarity, and width. Master and Slave modes are supported. PSP can
be programmed to be either full or half duplex.
formats. To allow flexibility the PSP format allows I2Sx_FRM to be programmable in
direction, delay, polarity, and width. Master and Slave modes are supported. PSP can
be programmed to be either full or half duplex.
The I2Sx_CLK function behavior varies between each format. PSP lets programmers
choose which edge of I2Sx_CLK to use for switching Transmit data, and for sampling
Receive data. In addition, programmers can control the idle state for I2Sx_CLK and the
number of active clocks that precede and follow the data transmission.
choose which edge of I2Sx_CLK to use for switching Transmit data, and for sampling
Receive data. In addition, programmers can control the idle state for I2Sx_CLK and the
number of active clocks that precede and follow the data transmission.
The PSP format provides programmability for several parameters that determine the
transfer timings between data samples. There are four possible serial clock sub-modes,
depending on the I2Sx_CLK edges selected for driving data and sampling received
data, and the selection of idle state of the clock.
transfer timings between data samples. There are four possible serial clock sub-modes,
depending on the I2Sx_CLK edges selected for driving data and sampling received
data, and the selection of idle state of the clock.
For the PSP format, the Idle and Disable modes of the I2Sx_DATAOUT, I2Sx_CLK, and
I2Sx_FRM are programmable by means of the SSPSP.ETDS, SSPSP.SCMODE and
SSPSP.SFRMP bits. When Transmit data is ready, the I2Sx_CLK will remain in its Idle
state for the number of serial clock (I2Sx_CLK) clock periods programmed within the
Start Delay (SSPSP.STRTDLY) field. I2Sx_CLK will then start toggling, I2Sx_DATAOUT
will remain in the idle state for the number of cycles programmed within the Dummy
Start (SSPSP.DMYSTRT) field. The I2Sx_FRM signal will be asserted after the number of
half-clocks programmed in the SSPSP.SFRDLY field. The I2Sx_FRM signal will remain
asserted for the number of clocks programmed within the SSPSP.SFRMWDTH then de-
assert. Four to 32 bits can be transferred per frame. Once the last bit (LSB) is
transferred, the I2Sx_CLK will continue toggling based off the Dummy Stop
(SSPSP.DMYSTOP) field. I2Sx_DATAOUT either retains the last value transmitted or is
forced to zero, depending on the value programmed within the End of Transfer Data
State (SSPSP.ETDS) field, when the controller goes into Idle mode, unless the
Enhanced SSP port is disabled or reset (which forces I2Sx_DATAOUT to zero).
I2Sx_FRM are programmable by means of the SSPSP.ETDS, SSPSP.SCMODE and
SSPSP.SFRMP bits. When Transmit data is ready, the I2Sx_CLK will remain in its Idle
state for the number of serial clock (I2Sx_CLK) clock periods programmed within the
Start Delay (SSPSP.STRTDLY) field. I2Sx_CLK will then start toggling, I2Sx_DATAOUT
will remain in the idle state for the number of cycles programmed within the Dummy
Start (SSPSP.DMYSTRT) field. The I2Sx_FRM signal will be asserted after the number of
half-clocks programmed in the SSPSP.SFRDLY field. The I2Sx_FRM signal will remain
asserted for the number of clocks programmed within the SSPSP.SFRMWDTH then de-
assert. Four to 32 bits can be transferred per frame. Once the last bit (LSB) is
transferred, the I2Sx_CLK will continue toggling based off the Dummy Stop
(SSPSP.DMYSTOP) field. I2Sx_DATAOUT either retains the last value transmitted or is
forced to zero, depending on the value programmed within the End of Transfer Data
State (SSPSP.ETDS) field, when the controller goes into Idle mode, unless the
Enhanced SSP port is disabled or reset (which forces I2Sx_DATAOUT to zero).
With the assertion of I2Sx_FRM, Receive data is simultaneously driven from the
peripheral on I2Sx_DATAIN, most significant bit first. Data transitions on I2Sx_CLK
based on the Serial Clock Mode selected and is sampled by the controller on the
opposite edge. When the Enhanced SSP is a master to the frame synch (I2Sx_FRM)
and a slave to the clock (I2Sx_CLK), then at least three extra clocks (I2Sx_CLKs) will
be needed at the beginning and end of each block of transfers to synchronize control
signals from the APB clock domain into the SSP clock domain (a block of transfers is a
group of back-to-back continuous transfers).
peripheral on I2Sx_DATAIN, most significant bit first. Data transitions on I2Sx_CLK
based on the Serial Clock Mode selected and is sampled by the controller on the
opposite edge. When the Enhanced SSP is a master to the frame synch (I2Sx_FRM)
and a slave to the clock (I2Sx_CLK), then at least three extra clocks (I2Sx_CLKs) will
be needed at the beginning and end of each block of transfers to synchronize control
signals from the APB clock domain into the SSP clock domain (a block of transfers is a
group of back-to-back continuous transfers).