Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
2816
Datasheet
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The DMA will wait for either the Transmit or Receive Service requests.
•
If the Transmit/Receive byte length is not an even multiple of the transfer burst
size, a trailing byte condition may occur.
size, a trailing byte condition may occur.
21.7.2
Trailing Bytes in the Receive FIFO
When the number of samples in the Receive FIFO is less than its FIFO trigger threshold
level, and no additional data is received, the remaining bytes are called trailing bytes.
Trailing bytes can be handled by either the DMA or the processor, as indicated by the
SSCR1.TRAIL bit. Trailing bytes are identified by means of a timeout mechanism and
the existence of data within the Receive FIFO.
level, and no additional data is received, the remaining bytes are called trailing bytes.
Trailing bytes can be handled by either the DMA or the processor, as indicated by the
SSCR1.TRAIL bit. Trailing bytes are identified by means of a timeout mechanism and
the existence of data within the Receive FIFO.
21.7.2.1
Timeout
A timeout condition exists when the Receive FIFO has been idle for a period of time (in
APB clocks) defined by the value programmed within the Timeout register (SSTO).
When a timeout occurs, the receiver timeout interrupt SSSR.TINT bit will be set to a 1,
and if the Timeout Interrupt is enabled SSCR1.TINTE=1, a Timeout Interrupt will occur
to signal the processor that a timeout condition has occurred. The timeout timer is
reset after a new sample is received. Once the SSSR.TINT bit is set it must be cleared
by software by writing a 1 to it. Clearing this bit also causes the Timeout Interrupt, if
enabled, to be de-asserted.
APB clocks) defined by the value programmed within the Timeout register (SSTO).
When a timeout occurs, the receiver timeout interrupt SSSR.TINT bit will be set to a 1,
and if the Timeout Interrupt is enabled SSCR1.TINTE=1, a Timeout Interrupt will occur
to signal the processor that a timeout condition has occurred. The timeout timer is
reset after a new sample is received. Once the SSSR.TINT bit is set it must be cleared
by software by writing a 1 to it. Clearing this bit also causes the Timeout Interrupt, if
enabled, to be de-asserted.
21.7.2.2
Peripheral Trailing Byte Interrupt
It is possible for the DMA to reach the end of its Descriptor chain while removing
Receive FIFO data. When this happens, the processor is forced to take over because
the DMA can no longer service the Enhanced SSP request until a new chain is linked.
When the DMA has reached the end of its Descriptor chain, and there is data in the
receive FIFO, the Enhanced SSP will do the following:
Receive FIFO data. When this happens, the processor is forced to take over because
the DMA can no longer service the Enhanced SSP request until a new chain is linked.
When the DMA has reached the end of its Descriptor chain, and there is data in the
receive FIFO, the Enhanced SSP will do the following:
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Sets the peripheral trailing byte interrupt SSSR.PINT bit to 1
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Asserts the Enhanced SSP Interrupt to signal to the processor that a Peripheral
Trailing Byte Interrupt condition has occurred (if SSCR1.PINTE=1 to enable the
interrupt).
Trailing Byte Interrupt condition has occurred (if SSCR1.PINTE=1 to enable the
interrupt).
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Sets the SSSR.EOC status bit which must be cleared by software. If more data is
received after the EOC bit was set (and EOC bit is still set), then the SSSR.PINT bit
will be set to a 1.
received after the EOC bit was set (and EOC bit is still set), then the SSSR.PINT bit
will be set to a 1.
Once the SSSR.PINT bit is set, it must be cleared by software by writing a 1 to it.
Clearing the SSSR.PINT bit also de-asserts the Peripheral Interrupt if it has been
enabled (SSCR1.PINTE=1).
Clearing the SSSR.PINT bit also de-asserts the Peripheral Interrupt if it has been
enabled (SSCR1.PINTE=1).
The remaining bytes must then be removed by means of a processor I/O as described
in the processor-based method below, or by reprogramming a new Descriptor chain
and restarting the DMA. Programmers need to be aware of this possibility. Refer to the
DMA chapter for details on Descriptor programming and “end of chain” events.
in the processor-based method below, or by reprogramming a new Descriptor chain
and restarting the DMA. Programmers need to be aware of this possibility. Refer to the
DMA chapter for details on Descriptor programming and “end of chain” events.