Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
288
Datasheet
12.3.5
DTR3 (DTR3)—Offset 4h
DRAM Timing Register 3
Access Method
Default: 06406255h
3
0h
RO
Rsvd_3_DTR2:
Reserved
2:0
4h
RW
tRRDR:
Read to Read DQ delay, different ranks, same DIMM 0h - Reserved 1h - 6 DRAM
Clocks (DDR3) 2h - 7 DRAM Clocks (LPDDR2-800, 1066. LPDDR3-1333) 3h - 8 DRAM
Clocks 4h - 9 DRAM Clocks 5h - 10 DRAM Clocks 6h - 11 DRAM Clocks Others - Reserved
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 1 0 1 0 1
Rsvd_31_D
TR3
DE
RA
TES
TA
T
DE
RA
TE
OVR
ENDRA
T
E
PW
DDL
Y
tX
P
Rsvd_21
_17_D
TR3
tWRSR
Rsvd_12_D
TR3
tRWSR
Rsvd_7_D
TR3
tWRDD
Rsvd_3_D
TR3
tWRDR
Bit
Range
Default &
Access
Field Name (ID): Description
31
0h
RO
Rsvd_31_DTR3:
Reserved
30
0h
RO
DERATESTAT:
Timing De-rating Status
29
0h
RW
DERATEOVR:
Enabled Timing De-rating Override
28
0h
RW
ENDRATE:
Enabled Dynamic Timing De-rating
27:24
6h
RW
PWDDLY:
RD/WR command to Power-down delay. Non-JEDEC delay for performance
enhancement. Delay = PWDDLY x 4 DRAM Clocks.
23:22
1h
RW
tXP:
Delay from CKE asserted high to any DRAM command 0h - 2 DRAM Clocks (DDR3-
800 2N) 1h - 3 DRAM Clocks (DDR3-800 1N) (DDR3-1066, 1333 2N) (LPDDR2-800) 2h
- 4 DRAM Clocks (DDR3-1066, 1333 1N) (DDR3-1600 2N) (LPDDR2-1066) 3h - 5 DRAM
Clocks (DDR3-1600 1N) (LPDDR3-1333)
21:17
0h
RO
Rsvd_21_17_DTR3:
Reserved