Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

293

DRAM Refresh Control

Default: 03012CA7h

5:4

1h

RW

Tristate Command and Address Bus to DRAM 0h - CMD/ADDR are never 

tristated. 1h - CMD/ADDR are tristated only when all CKE are low. 2h - CMD/ADDR are 

tristated when no valid command. 3h - CMD/ADDR are tristated when no valid command 

but may never be tristated for less than 2 DRAM clocks. This mode is only valid when 

tCMD is set to 0h (1N mode).

3:1

0h

RO

Reserved

0

1h

RW

Tristate Chip-Select 0 - Never tristate. 1 - TriState DRAM CS# pins from SRE 

to SRX+tXS. Note: DDRIO may tristate during SR so this adds on the boundries.

Message Bus Register

(Size: 32 bits)

Op Codes:
h - Read, h - Write

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 1

Rsvd_31_27

_D

RFC

CU

R

E

FR

A

T

E

Rsvd_23_22

_D

FRC

RE

FD

B

TCLR

REFS

KWDIS

Rsvd_19_18

_D

RFC

REFCNTMAX

Rsvd

_15

_D

RFC

tREFI

REFWMPNC

REFWMHI

REFWML

O

31:27

0h

RO

Reserved

26:24

3h

RO

Current Refresh Rate This value is updated by the Dunit TQ Poll logic after 

executing a Mode Register Read Command to the DRAM Device Temperature Mode 

Register (MR4). 0h - 4x tREFI, Low temperature operating limit exceeded 1h - 4x tREFI 

2h - 2x tREFI 3h - 1x tREFI ((= 85C) 4h - 0.5x tREFI (LPDDR3) 5h - 0.25x tREFI, do not 

de-rate AC timing 6h - 0.25x tREFI, de-rate AC timing 7h - 0.25x tREFI, High 

temperature operating limit exceeded Note: This is an LPDDR feature only.

23:22

0h

RO

Reserved

21

0h

RW

Clear Refresh Debit before SR Entry When this bit is set, if enough REF 

commands are pulled-in, Dunit will not send additional REF commands before SR Entry. 

0h - Disabled 1h - Enabled 

20

0h

RW

Refresh counters may be increased in 2 policies - skewed or 

simultaneously. 0h - counters are updated per rank every 1/4 tREFI period. 1h - all 

counters are updated every tREFI.