Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

291

31

28

24

20

16

12

8

4

0

0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EN

CO

RECLK

G

A

T

E

E

N

CK

TR

I

ENP

H

Y

C

LKG

A

TE

RE

U

TCLKGTDIS

Rsvd_27_DPMC0

BLMODE

DI

SPW

R

DN

CLK

G

TD

IS

DY

N

S

R

E

N

Rsvd_22_DPMC0

PRE

A

PWDEN

PC

LS

WK

OK

Rsvd_19_DPMC0

PCLS

TO

Rsvd_15

_13_DPMC0

PM

OP

SRE

D

LY

31

0h

RW

Enable Core Clock Gate During SR 0h - Core clock gating is 

disabled. 1h - Dunit enables the generic_clkreq_fsm during Self Refresh. The Dunit will 

re-enables the clocks upon Self Refresh exit. 

30

0h

RW

Enable CK/CKB TriState During PowerDown 0h - Disable CK/CKB Tristate 

During Powerdown. 1h - Enable CK/CKB Tristate During Powerdown. Note: This is an 

LPDDR feature only, for DDR3 bit should be set to 0. 

29

0h

RW

Enable PHY Clock Gate During SR 0h - PHY clock gating is disabled. 

1h - Dunit will drive the dun_cck_clkreq signal low to turn off the 1x and 2x clock trees 

from the CCK unit to the DDRO PHY during Self Refresh. The Dunit will re-enables the 

clocks upon Self Refresh exit. 

28

0h

RW

REUT Clock Gate Disable 0h - REUT clock is gated when DCO.PMICTL 

is set to 0. 1h - REUT clock is upgated, overriding the DCO.PMICTL config bit. Note: The 

DCO.REUTLOCK bit overrides this bit. 

27

1h

RO

Reserved

26

0h

RW

Burst Length Mode. Selects the DDR3 Burst Length mode: 0h - BL8 Fixed 1h 

- BL8/BC4 On-the-Fly Note: This bit should be zero for LPDDR2 and LPDDR3. 

25

1h

RW

Disable Power Down. Setting this bit to 1 will block CKE high-)low 

transitions. May be used by BIOS during init flow and should be set to 0 for functional 

mode. 0h - The Dunit dynamically controls the CKE pins to place the DRAM device in 

power down mode. 1h - The Dunit constantly drives the CKE pins high. 

24

1h

RW

Clock Gating Disabled. Setting this bit to 0 allows a large number of 

internal Dunit clocks to be gated when there is no activity in order to save power. When 

set to 1, internal clock-gating is disabled. 0h - Enable 1h - Disable 

23

0h

RW

Dynamic Self-Refresh Enable. Setting this bit to 1, enables automatic SR 

command to DRAM and PM message to DDRIO when the PMI bus is idle, all pending 

requests have been served and the and PMI status is less than 2, SREDLY has timed-

out, and all JEDEC requirements are satisfied. This register may be changed by BIOS/

FW on-the-fly. 

22

0h

RO

Reserved

21

0h

RW

Send Precharge All Command to a Rank before PD-Enter. Setting this bit 

to 1 will allow sending a PREA command before PDE command. 0h - Disable 1h - Enable