Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
368
Datasheet
13.6.19
CPU_SOFT_STRAPS—Offset 7Ch
Register for BIOS software configurable CPU Power on Reset Configuration. This
register survives CPU-only reset and SOC Warm reset. BIOS can access is register
using CFC/CF8 mechanism. Accessible through MSG Bus Port 04h.
Access Method
16
0h
RW
PWRGINTREN_LISLAND_RENDER:
power gate Interrupt sts for local standby island
RENder. Not used for VLV
15
0h
RW
PWRGATEINTREN_RESERVED12:
Reserved
14
0h
RW
PWRGATEINTREN_RESERVED11:
Reserved
13
0h
RW
PWRGATEINTREN_RESERVED10:
Reserved
12
0h
RW
PWRGATEINTREN_RESERVED9:
Reserved
11
0h
RW
PWRGATEINTREN_RESERVED8:
Reserved
10
0h
RW
PWRGATEINTREN_RESERVED7:
Reserved
9
0h
RW
PWRGATEINTREN_RESERVED6:
Reserved
8
0h
RW
PWRGATEINTREN_RESERVED5:
Reserved
7
0h
RW
PWRGATEINTREN_RESERVED4:
Reserved
6
0h
RW
PWRGATEINTREN_RESERVED3:
Reserved
5
0h
RW
PWRGATEINTREN_RESERVED2:
Reserved
4
0h
RW
PWRGATEINTREN_RESERVED1:
Reserved
3
0h
RW
PWRGATEINTREN_DISPLAY:
power gate interrupt status for display, no control hook
for DPIO
2
0h
RW
PWRGATEINTREN_RESERVED0:
Reserved
1
0h
RW
PWRGATEINTREN_MEDIA:
power gate interrupt status for media
0
0h
RW
PWRGATEINTREN_RENDER:
power gate interrupt status for RENder
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write