Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

4418

Datasheet

The Transmit Data Request interrupt occurs when the transmit FIFO is half empty or 
more than half empty. The interrupt is cleared as soon as the Transmit Holding Register 
is written (1 to 16 characters may be written to the transmit FIFO while servicing the 
interrupt) or the Interrupt Identification Register is read.

With the FIFOs enabled (FIFO Control register, bit 0 = 1b), setting Interrupt Enable 
register (IER), bits 3:0 = 000b puts the serial port in the FIFO polled mode of 
operation. Since the receiver and the transmitter are controlled separately, either one 
or both may be in the polled mode of operation. In this mode, software checks receiver 
and transmitter status through the Line Status Register (LSR). As stated in the register 
description:

•

LSR[0] is set as long as there is one byte in the receiver FIFO.

•

LSR[1] through LSR[4] specify which error(s) has occurred for the character at the 
top of the FIFO. Character error status is handled the same way as interrupt mode. 
The Interrupt Identification Register is not affected since IER[2] = 0b.

•

LSR[5] indicates when the transmitter FIFO needs data.

•

LSR[6] indicates that both the transmitter FIFO and shift register are empty.

•

LSR[7] indicates whether there are any errors in the receiver FIFO.

The base I/O address for the COM1 UART is fixed to 3F8h.

The legacy interrupt assigned to the COM1 UART is fixed to IRQ4.

The COM1 UART may be enabled or disabled using the UART_CONT.COM1EN register 
bit. By default, the UART is disabled.

It is recommended that the UART be disabled during normal platform operation since it 
is a PIO device and, as such, can prevent residency in lower power states by the 
processor.