Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

4419

There are 12 registers associated with the UART. These registers share eight address 
locations in the IO address space. 

 shows the registers and their addresses as 

offsets of a base address. Note that the state of the COM1_LCR.DLAB register bit, 
which is the most significant bit (MSB) of the Serial Line Control register, affects the 
selection of certain of the UART registers. The COM1_LCR.DLAB register bit must be set 
high by the system software to access the Baud Rate Generator Divisor Latches.

1.

These registers are consolidated in the Receiver Buffer / Transmitter Holding Register 

(COM1_RX_TX_BUFFER)

2.

These registers are consolidated in the Interrupt Enable Register (COM1_IER)

3.

These registers are consolidated in the Interrupt Identification / FIFO Control Register (COM1_IIR)

4.

These registers are implemented but unused since the UART signals related to modem interaction are 

not implemented.

§ 

0h

0b

RO

Receiver Buffer

1

0h

0b

WO

Transmitter Holding

1

0h

1b

RW

Divisor Latch LSB (Lowest Significant Bit)

1

1h

0b

RW

Interrupt Enable

2

1h

1b

RW

Divisor Latch MSB (Most Significant Bit)

2

2h

xb

RO

Interrupt Identification

3

2h

xb

WO

FIFO Control

3

3h

xb

RW

Line Control

4h

xb

RW

Modem Control

4

5h

xb

RO

Line Status

6h

xb

RO

Modem Status

4

7h

xb

RW

Scratchpad