Intel E3815 FH8065301567411 Data Sheet

Product codes

FH8065301567411

Intel

Atom™ Processor E3800 Product Family

4420

Datasheet

32.6

PCU iLB UART IO Registers

32.6.1

Receiver Buffer / Transmitter Holding Register

(COM1_Rx_Tx_Buffer)—Offset 3F8h

This register is a combination of three registers: the receiver buffer register (RBR) that

is a read-only register when DLAB=0, the transmitter holding register (THR) that is a

write-only register when DLAB=0 and the divisor latch LSB (DLL) register when

DLAB=1.

Access Method

Default: 00h

Table 307.

Summary of PCU iLB UART

I/O Registers—

Offset

Size

Register ID—Description

Default

Value

3F8h

“Receiver Buffer / Transmitter Holding Register (COM1_Rx_Tx_Buffer)—Offset

3F8h” on page 4420

00h

3F9h

“Interrupt Enable Register (COM1_IER)—Offset 3F9h” on page 4421

00h

3FAh

“Interrupt Identification / FIFO Control Register (COM1_IIR)—Offset 3FAh” on

page 4422

01h

3FBh

“Line Control Register (COM1_LCR)—Offset 3FBh” on page 4423

00h

3FCh

“Modem Control Register (COM1_MCR)—Offset 3FCh” on page 4424

00h

3FDh

“Line Status Register (COM1_LSR)—Offset 3FDh” on page 4425

60h

3FEh

“Modem Status Register (COM1_MSR)—Offset 3FEh” on page 4426

00h

3FFh

“Scratchpad Register (COM1_SCR)—Offset 3FFh” on page 4428

00h

Type:

I/O Register

(Size: 8 bits)

COM1_Rx_Tx_Buffer:

3F8h

RBR_THR_DLL