Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

448

Datasheet

B838–B83Bh

4

“MIPIC_VERT_SYNC_PADDING_COUNT—Offset B838h” on page 560

00000000h

B83C–B83Fh

4

“MIPIC_VERT_BACK_PORCH_COUNT—Offset B83Ch” on page 561

00000000h

B840–B843h

4

“MIPIC_VERT_FRONT_PORCH_COUNT—Offset B840h” on page 562

00000000h

B844–B847h

4

“MIPIC_HIGH_LOW_SWITCH_COUNT—Offset B844h” on page 562

00000000h

B848–B84Bh

4

“MIPIC_DPI_CTRL_REG—Offset B848h” on page 563

00000000h

B84C–B84Fh

4

“MIPIC_DPI_DATA_REGISTER—Offset B84Ch” on page 564

00000000h

B850–B853h

4

“MIPIC_INIT_COUNT_REGISTER—Offset B850h” on page 565

00000000h

B854–B857h

4

“MIPIC_MAX_RETURN_PKT_SIZE_REGISTER—Offset B854h” on

00000000h

B858–B85Bh

4

“MIPIC_VIDEO_MODE_FORMAT_REGISTER—Offset B858h” on

00000000h

B85C–B85Fh

4

“MIPIC_EOT_DISABLE_REGISTER—Offset B85Ch” on page 567

00000000h

B860–B863h

4

“MIPIC_LP_BYTECLK_REGISTER—Offset B860h” on page 569

00000000h

B864–B867h

4

“MIPIC_LP_GEN_DATA_REGISTER—Offset B864h” on page 570

00000000h

B868–B86Bh

4

“MIPIC_HS_GEN_DATA_REGISTER—Offset B868h” on page 570

00000000h

B86C–B86Fh

4

“MIPIC_LP_GEN_CTRL_REGISTER—Offset B86Ch” on page 570

00000000h

B870–B873h

4

“MIPIC_HS_GEN_CTRL_REGISTER—Offset B870h” on page 571

00000000h

B874–B877h

4

“MIPIC_GEN_FIFO_STAT_REGISTER—Offset B874h” on page 572

1E060606h

B878–B87Bh

4

“MIPIC_HS_LS_DBI_ENABLE_REG—Offset B878h” on page 574

00000000h

B87C–B87Fh

4

“MIPIC_RESERVED—Offset B87Ch” on page 574

00000000h

B880–B883h

4

“MIPIC_DPHY_PARAM_REG—Offset B880h” on page 575

0B061A04h

B884–B887h

4

“MIPIC_DBI_BW_CTRL_REG—Offset B884h” on page 576

00000000h

B888–B88Bh

4

“MIPIC_CLK_LANE_SWITCHING_TIME_CNT—Offset B888h” on

00000000h

B88C–B88Fh

4

“MIPIC_STOP_STATE_STALL—Offset B88Ch” on page 577

00000000h

B890–B893h

4

“MIPIC_INTR_STAT_REG_1—Offset B890h” on page 578

00000000h

B894–B897h

4

“MIPIC_INTR_EN_REG_1—Offset B894h” on page 578

00000000h

B904–B907h

4

“MIPIC_CTRL—Offset B904h” on page 579

00000000h

B908–B90Bh

4

“MIPIC_DATA_ADD—Offset B908h” on page 580

00000000h

B90C–B90Fh

4

“MIPIC_DATA_LEN—Offset B90Ch” on page 580

00000000h

B910–B913h

4

“MIPIC_CMD_ADD—Offset B910h” on page 581

00000000h

B914–B917h

4

“MIPIC_CMD_LEN—Offset B914h” on page 582

00000000h

B918–B91Bh

4

“MIPIC_RD_DATA_RETURN0—Offset B918h” on page 582

00000000h

B91C–B91Fh

4

“MIPIC_RD_DATA_RETURN1—Offset B91Ch” on page 583

00000000h

B920–B923h

4

“MIPIC_RD_DATA_RETURN2—Offset B920h” on page 583

00000000h

B924–B927h

4

“MIPIC_RD_DATA_RETURN3—Offset B924h” on page 584

00000000h

B928–B92Bh

4

“MIPIC_RD_DATA_RETURN4—Offset B928h” on page 585

00000000h

B92C–B92Fh

4

“MIPIC_RD_DATA_RETURN5—Offset B92Ch” on page 585

00000000h

B930–B933h

4

“MIPIC_RD_DATA_RETURN6—Offset B930h” on page 586

00000000h

B934–B937h

4

“MIPIC_RD_DATA_RETURN7—Offset B934h” on page 586

00000000h

Table 170.

Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default Value