Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

446

Datasheet

6210–6213h

4

“RAMCLK_GATE_D—Offset 6210h” on page 495

00000000h

6500–6503h

4

“FW_BLC_SELF—Offset 6500h” on page 498

00000000h

6504–6507h

4

“MI_ARB—Offset 6504h” on page 499

00000000h

6508–650Bh

4

“CZCLK_CDCLK_FREQ_RATIO—Offset 6508h” on page 499

00000077h

650C–650Fh

4

“GCI_CONTROL—Offset 650Ch” on page 503

00004000h

6510–6513h

4

“GMBUSFREQ—Offset 6510h” on page 504

000000A0h

A000–A003h

4

“DPALETTE_A—Offset A000h” on page 505

00000000h

A800–A803h

4

“DPALETTE_B—Offset A800h” on page 506

00000000h

B000–B003h

4

“MIPIA_DEVICE_READY_REG—Offset B000h” on page 506

00000000h

B004–B007h

4

“MIPIA_INTR_STAT_REG—Offset B004h” on page 507

00000000h

B008–B00Bh

4

“MIPIA_INTR_EN_REG—Offset B008h” on page 509

00000000h

B00C–B00Fh

4

“MIPIA_DSI_FUNC_PRG__REG—Offset B00Ch” on page 511

00000001h

B010–B013h

4

“MIPIA_HS_TX_TIMEOUT_REG—Offset B010h” on page 512

00000000h

B014–B017h

4

“MIPIA_LP_RX_TIMEOUT_REG—Offset B014h” on page 513

00000000h

B018–B01Bh

4

“MIPIA_TURN_AROUND_TIMEOUT_REG—Offset B018h” on page 514

00000000h

B01C–B01Fh

4

“MIPIA_DEVICE_RESET_TIMER—Offset B01Ch” on page 515

00000000h

B020–B023h

4

“MIPIA_DPI_RESOLUTION_REG—Offset B020h” on page 515

00000000h

B024–B027h

4

“MIPIA_DBI_RESOLUTION_REG—Offset B024h” on page 516

00000000h

B028–B02Bh

4

“MIPIA_HORIZ_SYNC_PADDING_COUNT—Offset B028h” on page 516

00000000h

B02C–B02Fh

4

“MIPIA_HORIZ_BACK_PORCH_COUNT—Offset B02Ch” on page 517

00000000h

B030–B033h

4

“MIPIA_HORIZ_FRONT_PORCH_COUNT—Offset B030h” on page 518

00000000h

B034–B037h

4

“MIPIA_HORIZ_ACTIVE_AREA_COUNT—Offset B034h” on page 519

00000000h

B038–B03Bh

4

“MIPIA_VERT_SYNC_PADDING_COUNT—Offset B038h” on page 519

00000000h

B03C–B03Fh

4

“MIPIA_VERT_BACK_PORCH_COUNT—Offset B03Ch” on page 520

00000000h

B040–B043h

4

“MIPIA_VERT_FRONT_PORCH_COUNT—Offset B040h” on page 521

00000000h

B044–B047h

4

“MIPIA_HIGH_LOW_SWITCH_COUNT—Offset B044h” on page 521

00000000h

B048–B04Bh

4

“MIPIA_DPI_CTRL_REG—Offset B048h” on page 522

00000000h

B04C–B04Fh

4

“MIPIA_DPI_DATA_REGISTER—Offset B04Ch” on page 523

00000000h

B050–B053h

4

“MIPIA_INIT_COUNT_REGISTER—Offset B050h” on page 524

00000000h

B054–B057h

4

“MIPIA_MAX_RETURN_PKT_SIZE_REGISTER—Offset B054h” on

00000000h

B058–B05Bh

4

“MIPIA_VIDEO_MODE_FORMAT_REGISTER—Offset B058h” on

00000000h

B05C–B05Fh

4

“MIPIA_EOT_DISABLE_REGISTER—Offset B05Ch” on page 526

00000000h

B060–B063h

4

“MIPIA_LP_BYTECLK_REGISTER—Offset B060h” on page 528

00000000h

B064–B067h

4

“MIPIA_LP_GEN_DATA_REGISTER—Offset B064h” on page 529

00000000h

B068–B06Bh

4

“MIPIA_HS_GEN_DATA_REGISTER—Offset B068h” on page 529

00000000h

B06C–B06Fh

4

“MIPIA_LP_GEN_CTRL_REGISTER—Offset B06Ch” on page 529

00000000h

B070–B073h

4

“MIPIA_HS_GEN_CTRL_REGISTER—Offset B070h” on page 530

00000000h

Table 170.

Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default Value