Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

475

GMBUS Data Buffer gmbus data buffer (gmbus_register.v reg_gmbus3)

Default: 00000000h

12

0b

RO

This bit indicates that an event that 

causes a GMBUS interrupt has occurred.  

0 = The conditions that could cause a GMBUS interrupt have not occurred or this bit has 

been cleared by software assertion of the SW_CLR_INT bit. 

1 = GMBUS interrupt event occurred. This interrupt must have been one of the types 

enabled in the GMBUS4 register. 

[DevCDV, DevCTG]: Reserved  

AccessType: Read Only

11

1b

RO

This provides a method of detecting 

when the current software client routine can proceed with the next step in a sequence of 

GMBUS operations. This data handshake bit is used in conjunction with the SW_RDY bit. 

When this bit is changed to asserted by the GMBUS controller, it results in the de-

assertion of the SW_RDY bit.  

0 = Condition required for assertion has not occurred or when this bit was a one and: 

SW_RDY bit has been asserted. 

During a GMBUS read transaction, after the each read of the data register.  

During a GMBUS write transaction, after each write of the data register. 

SW_CLR_INT bit has been cleared. 

1 = This bit is asserted under the following conditions: 

After a reset or when the transaction is aborted by the setting of the SW_CLR_INT bit.  

When an active GMBUS cycle has terminated with a STOP. 

When during a GMBUS write transaction, the data register needs and can accept 

another four bytes of data.  

During a GMBUS read transaction, this bit is asserted when the data register has four 

bytes of new data or the read transaction DATA phase is complete and the data register 

contains the last few bytes of the read data.  

This bit resumes to normal operation when the SW_CLR_INT bit is written to a 0.  

AccessType: Read Only

10

0b

RO

Was previously called Slave Acknowledge Timeout 

Error SATOER. 

0 = No bus error has been detected or SW_CLR_INT has been written as a zero since 

the last bus error. 

1 = Set by hardware if any expected device acknowledge is not received from the slave 

within the timeout.  

AccessType: Read Only

9

0b

RO

This is a status bit that indicates whether the 

GMBUS controller is in an IDLE state or not. 

0 = The GMBUS controller is currently IDLE. 

1 = This indicates that the bus is in START, ADDRESS, INDEX, DATA, WAIT, or STOP 

Phase. Set when GMBUS hardware is not IDLE.  

AccessType: Read Only

8:0

0b

RO

Can be used to determine the number of 

bytes currently transmitted/received by the GMBUS controller hardware. Set to zero at 

the start of a GMBUS transaction data transfer and incremented after the completion of 

each byte of the data phase. Note that because reads have internal storage, the byte 

count on a read operation may be ahead of the data that has been accepted from the 

data register.  

AccessType: Read Only

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h