Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
499
14.10.39 MI_ARB—Offset 6504h
Display Arbiter
Access Method
Default: 00000000h
14.10.40 CZCLK_CDCLK_FREQ_RATIO—Offset 6508h
Display CZCLK/CDCLK FREQ Ratio for RMBUS sync
Access Method
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0b
RW
RESERVED:
Reserved.
15
0b
RW
CSPWRDWNEN:
1 = Dispaly FIFO can go into max_fifo configuration if only one plane
A/B is enabled and all other planes, including overlay, are off.
0 = Dont put display FIFO in max_fifo configuration
14:0
0b
RW
RESERVED_1:
Reserved.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RES
E
RVE
D
DI
SPLA
Y_TRICKLE_FEED_DISABL
E
RES
E
RV
ED_1
Bit
Range
Default &
Access
Field Name (ID): Description
31:3
0b
RW
RESERVED:
Reserved.
2
0b
RW
DISPLAY_TRICKLE_FEED_DISABLE:
1 Disable (Turn off trickle feed Display
request).
0 Enable (Default)
1:0
0b
RW
RESERVED_1:
Reserved.