Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
534
Datasheet
14.10.77 MIPIA_DPHY_PARAM_REG—Offset B080h
mipi A dphy parameter register
Access Method
Default: 0B061A04h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SE
RVED
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0b
RO
RESERVED:
Reserved.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0
RES
E
RVE
D
E
X
IT_ZERO
_
CO
UNT
RES
E
RV
ED_1
TRA
IL_CO
UNT
CLK
_
ZERO
_CO
U
NT
RES
E
RV
ED_2
P
R
EP
ARE
_
CO
UNT
Bit
Range
Default &
Access
Field Name (ID): Description
31:30
0b
RW
RESERVED:
Reserved.
29:24
001011b
RW
EXIT_ZERO_COUNT:
THS_0_TIM_UI_CNT and THS_EXIT_TIM_UI_CNT for dphy are
programmed as exit zero count by the processor
23:21
0b
RW
RESERVED_1:
Reserved.
20:16
00110b
RW
TRAIL_COUNT:
TCLK_POST_TIM_UI_CNT and TCLK_TRAIL_TIM_UI_CNT for dphy are
programmed as trail count by the processor
15:8
00011010b
RW
CLK_ZERO_COUNT:
TCLK_0_TIM_UI_CNT for dphy is programmed as clk zero count
by the processor
7:6
0b
RW
RESERVED_2:
Reserved.
5:0
000100b
RW
PREPARE_COUNT:
TCLK_PREP_TIM_UI_CNT and THS_PREP_TIM_UI_CNT for dphy are
programmed as prepare count by the processor