Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
535
14.10.78 MIPIA_DBI_BW_CTRL_REG—Offset B084h
mipi A DBI BW ctrl register
Access Method
Default: 00000000h
14.10.79 MIPIA_CLK_LANE_SWITCHING_TIME_CNT—Offset B088h
mipi A clk clane switching time counter
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BA
ND
WID
T
H
_
T
IM
E
R
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0b
RW
BANDWIDTH_TIMER:
DBI Bandwidth control Register. The bandwidth essential for
transmitting 16 long packets containing 252 bytes meant for DCS write memory
command is programmed in this register in terms of byte clocks. Based on the DSI
transfer rate and the number of lanes configured the time taken to transmit 16 long
packets in a DSI stream varies.
Note: The value programmed in this timer must be greater than the actual time taken to
carryout 16 long packets transmission in DSI stream plus the time taken to transmit two
blanking packets
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LS_H
S
_
S
S
W_CNT
H
S
_LS_P
W
R_SW_C
NT