Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

667

CRT port control (dprrega.v porthotst_aR)

Default: 00000000h

6:5

01b

RW

[DevVLVP] MBZ. This bit is the same as bit 19:18 in 61100h 

[DevCDV, DevCTG, DevBW, DevCL, DevBLC] CRT Hot plug Voltage Compare Value: 

Compare value for CRT hotplug detect Vref to determine whether the analog port is 

connected to a CRT. The voltage is forced at the beginning of the active region of the 

screen every 2 seconds. 

00 = A0,  

01 = B0, (Default) 

10 = C0 

11 = D0

4

0b

RW

[DevVLVP] MBZ. This bit is the same as bit 20 in 61100h 

[DevCDV, DevCTG, DevBW, DevCL, DevBLC] CRT Hot Plug Detect Delay: This bit 

determines the length of time between polling periods when the DAC/pipe are disabled 

0 = 1G cdclks (default) 

1 = 2G cdclks

3

0b

RW

[DevVLVP] MBZ 

[DevCDV, DevCTG, DevBW, DevCL, DevBLC] Force CRT detect trigger: Triggers a CRT 

hotplug/unplug detection cycle independent of the interrupt enable bit. Bits 5:8 of this 

register must be correctly programmed when forcing a trigger. This bit is automatically 

cleared after the detection is completed. The result of this trigger is reflected in bits 9:8 

of the port hotplug interrupt status register. The CRT interrupt status bit #11 in the hot 

plug status register (61114) will get set the first time Force CRC detect trigger is used 

after reset. Software must reset status after a force CRT detect trigger.  

0 = No trigger (Default) 

1 = Trigger

2

0b

RW

[DevVLVP] MBZ. This bit is the same as bit 17 in 61100h 

[DevCTG-B] CRT DAC hot plug detection reference voltage selection: 

0 = 325mv, bits[6:5] should be set to 01 (Default) 

1 = 475mv, bits[6:5] should be set to 11 

1:0

0b

RW

mbz

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h