Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

669

23

0b

RO

[DevVLVP] This read-only bit is used 

only in ports that use TMDS encoding. It reflects the state of the pipe B audio interrupt 

request for HDCP when bit 1 of this register is set. This pin signal is active high. It does 

not feed into the first line interrupt status register. 

1 = HDCP invocation requested from audio 

0 = HDCP disable requested from audio  

AccessType: Read Only

22:21

0b

RW/1C

[DevCTG] This 

reflects hot plug interrupt status on DisplayPort D. Graphics software must write a one 

to these bits to clear the status. This bit is used for either monitor hotplug/unplug or for 

notification of a sink event. This bit feeds into the first line interrupt status register when 

bit 27 of the hotplug enable status register is set. 

00 = DisplayPort D Hot Plug event not detected  

1x = DisplayPort D long pulse Hot Plug event detected 

X1 = DisplayPort D short pulse Hot Plug event detected  

AccessType: One to Clear

20:19

0b

RW/1C

[DevCDV, DevCTG, 

DevELK] This reflects hot plug interrupt status on DisplayPort or HDMI C. Graphics 

software must write a one to these bits to clear the status. This bit is used for either 

monitor hotplug/unplug or for notification of a sink event. This bit feeds into the first line 

interrupt status register when bit 28 of the hotplug enable status register is set. 

Please note that these bits should be considered in conjunction with bit 28, the hot plug 

input buffer live state, when determining further action: if bit 28 = 0, the bits should be 

cleared and the port must be disabled.  

00 = DisplayPort/HDMI C Hot Plug event not detected  

1x = DisplayPort/HDMI C long pulse Hot Plug event detected 

X1 = DisplayPort C short pulse Hot Plug event detected  

AccessType: One to Clear

18:17

0b

RW/1C

[DevCDV, DevCTG, 

DevELK] This reflects hot plug interrupt status on DisplayPort B. Graphics software must 

write a one to these bits to clear the status. This bit is used for either monitor hotplug/

unplug or for notification of a sink event. This bit feeds into the first line interrupt status 

register when bit 29 of the hotplug enable status register is set. 

Please note that these bits should be considered in conjunction with bit 29, the hot plug 

input buffer live state, when determining further action: if bit 29 = 0, the bits should be 

cleared and the port must be disabled.  

00 = DisplayPort/HDMI B Hot Plug event not detected  

1x = DisplayPort/HDMI B long pulse Hot Plug event detected 

X1 = DisplayPort B short pulse Hot Plug event detected  

AccessType: One to Clear

16

0b

RO

[DevCDV, DevCTG, DevCL] This read-

only bit is used only in ports that use TMDS encoding. It reflects the state of the pipe A 

audio interrupt request for HDCP when bit 1 of this register is set. This pin signal is 

active high. It does not feed into the first line interrupt status register. 

1 = HDCP invocation requested from audio 

0 = HDCP disable requested from audio  

AccessType: Read Only

15

0b

RO

[DevCDV, DevCTG, DevCL] 

This read-only bit is only used on ports using audio. It reflects the state of audio HDCP 

request when bit 17 of this register is set if audio is enabled on this port. This pin signal 

is active high. This does not feed into the first line interrupt status register. 

1 = HDCP invocation requested from audio 

0 = HDCP disable requested from audio  

AccessType: Read Only

14

0b

RO

[DevCDV, DevCTG, DevCL] 

This read-only bit is only used on ports using audio. It reflects the state of audio HDCP 

request when bit 19 of this register is set if audio is enabled on this port. This pin signal 

is active high. This does not feed into the first line interrupt status register. 

1 = HDCP invocation requested from audio 

0 = HDCP disable requested from audio  

AccessType: Read Only

13:12

0b

RW

mbz