Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

670

Datasheet

11

0b

RW/1C

[DevCDV, DevCTG, DevBW, DevCL, DevBLC] 

This bit is set when a CRT hot plug or unplug event has been detected. A hot plug or 

unplug event is defined as the change in connection state of the CRT as determined by 

the hardware CRT detect sequence which is enabled through bit #9 (CRT hot plug 

interrupt enable) or bit #3 (Force CRT detect trigger) in the Port_HotPlug_En register 

0x61110. After reset, the CRT is considered unconnected even if physically connected 

until the first detect sequence occurs. Physically plugging or unplugging the CRT device 

will also be detected as a change of connection state. Writing a 1 to this bit clears it.  

0 =CRT Interrupt has not occurred 

1 = CRT Interrupt has occurred  

AccessType: One to Clear

10

0b

RW/1C

[DevCTG, DevBW, DevCL, DevBLC] This bit is 

set when a TV hot plug or unplug event has been detected. Reflects the state of bit 31 of 

the TV DAC state register, offset 68004-68007h. Software must write a one to these bits 

to clear the status. 

0 =TV Interrupt has not occurred 

1 = TV Interrupt has occurred  

AccessType: One to Clear

9:8

0b

RW/1C

[DevVLVP] MBZ. These info are recorded in 61100h ADPA 

register[25:24] 

[DevCDV, DevCTG, DevBW, DevCL, DevBLC] CRT Hot Plug Detection Status (read only): 

These bits are set when a CRT hot plug or unplug event has been detected.  

00 = No channels attached (default) 

01 = Blue channel only is attached 

10 = Green channel only is attached 

11 = Both blue and green channel attached  

AccessType: One to Clear

7

0b

RW

mbz

6

0b

RW/1C

[DevCTG] This bit is set when a 

transaction on AUX channel D has completed or timed out. This bit feeds into the first 

line interrupt status register when bit 29 of the AUX channel D control register is set. 

Writing a 1 to this bit clears it. 

0 = AUX channel D Interrupt has not occurred 

1 = AUX channel D Interrupt has occurred  

AccessType: One to Clear

5

0b

RW/1C

[DevCTG, DevCDV] This bit is set 

when a transaction on AUX channel C has completed or timed out. This bit feeds into the 

first line interrupt status register when bit 29 of the AUX channel C control register is 

set. Writing a 1 to this bit clears it. 

0 = AUX channel C Interrupt has not occurred 

1 = AUX channel C Interrupt has occurred  

AccessType: One to Clear

4

0b

RW/1C

[DevCTG, DevCDV] This bit is set 

when a transaction on AUX channel B has completed or timed out. This bit feeds into the 

first line interrupt status register when bit 29 of the AUX channel B control register is 

set. Writing a 1 to this bit clears it. 

0 = AUX channel B Interrupt has not occurred 

1 = AUX channel B Interrupt has occurred  

AccessType: One to Clear

3

0b

RW/1C

[DevCTG, DevCDV] This 

reflects hot plug interrupt status on SDVO port C. Graphics software must write a one to 

these bits to clear the status. This bit is used for either monitor hotplug/unplug or for 

notification of an HDCP state change request from the audio driver over SDVO only. This 

bit feeds into the first line interrupt status register when bit 25 of the hotplug enable 

status register is set. 

0 = SDVO Hot Plug event not detected 

1 = SDVO Hot Plug event detected  

AccessType: One to Clear