Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
671
14.11.26 SDVOHDMIB—Offset 61140h
Digital Display Port B Control Register HDMIB port control (dprrega.v sdvo_bQ)
Access Method
Default: 00000018h
2
0b
RW/1C
SDVO_B_HOT_PLUG_INTERRUPT_DETECT_STATUS:
[DevCTG, DevCDV] This
reflects hot plug interrupt status on SDVO port B. Graphics software must write a one to
these bits to clear the status. This bit is used for either monitor hotplug/unplug or for
notification of an HDCP state change request from the audio driver over SDVO only. This
bit feeds into the first line interrupt status register when bit 26 of the hotplug enable
status register is set.
0 = SDVO Hot Plug event not detected
1 = SDVO Hot Plug event detected
AccessType: One to Clear
1
0b
RW/1C
PIPE_A_AUDIO_INTERRUPT_DETECT_STATUS:
[DevCTG, DevCDV, DevCL] This
reflects a request for integrated HDCP state change set by audio driver and propagated
through the audio hardware. The graphics software must write a one to this bit to clear
the status. Upon clearing this bit, the audio ready bit is cleared in the audio registers.
The graphics software then must reset audio ready bit 14 in the audio control register,
offset 620B4h to 1 when the HDCP interrupt has been serviced. This bit feeds into the
first line interrupt status register when bit 24 of the hotplug enable status register is set
0 = Audio interrupt event not detected
1 = Audio interrupt event detected
AccessType: One to Clear
0
0b
RW/1C
PIPE_B_AUDIO_INTERRUPT_DETECT_STATUS:
[DevCTG, DevCDV, DevCL] This
reflects a request for integrated HDCP state change set by audio driver and propagated
through the audio hardware. The graphics software must write a one to this bit to clear
the status. Upon clearing this bit, the audio ready bit is cleared in the audio registers.
The graphics software then must reset audio ready bit 14 in the audio control register,
offset 620B4h to 1 when the HDCP interrupt has been serviced. This bit feeds into the
first line interrupt status register when bit 23 of the hotplug enable status register is set
0 = Audio interrupt event not detected
1 = Audio interrupt event detected
AccessType: One to Clear
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h