Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
693
14.11.39 PIPEA_PP_STATUS—Offset 61200h
PipeA Panel Power Status Register ([DevCL, DevCTG, DevCDV]) PP Status (dplrreg.v
panel_pwr_sr)
Access Method
Default: 08000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PA
N
E
L_
PO
W
E
R
_
O
N
_
S
TA
T
U
S
RE
QU
IRE_A
S
SET
_
ST
A
T
US
POWER_S
E
QUENCE_PROGRE
S
S
PO
W
E
R
_
CY
CLE
_
DELA
Y
_
AC
TI
VE
RE
S
E
R
V
E
D
INTER
N
A
L_SEQ
UENCE
_
ST
A
T
E_FOR_T
E
ST
_
D
EBUG
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RO
PANEL_POWER_ON_STATUS:
0 = Indicates that the panel power down sequencing
has completed. A power cycle delay may be currently active. It is safe and allowed to
program pipe timing and DPLL registers. If this bit is not a zero, it activates the register
write protect and writes to those registers will be ignored unless the write protect key
value is set in the panel sequencing control register.
1 = In conjunction with bits Power Sequence Progress field and Power Cycle Delay
Active, this bit set to a one indicates that the panel is currently powered up or is
currently in the power down sequence and it is unsafe to change the pipe timing and
DPLL registers for the pipe that is assigned to the embedded panel output.
If the embedded panel port is selected as the target for the panel control, Software is
responsible for enabling the LCD display by writing a 1 to the port enable bit only after
all pipe timing, DPLL registers are properly programmed, and the PLL has locked to the
reference signal.
This bit is cleared (set to 0) only after the panel power down sequencing is completed.