Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

713

PipeB Panel Power off Sequencing Delays ([DevVLVP]) PP Delay Off values (dplrreg.v 

DPLRppoff_sd)

Default: 00000000h

PipeB Panel Power Cycle Delay and Reference Divisor ([DevVLVP]) PP Divisor (dplrreg.v 

DPLRrefdiv_pp_cd)

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RE

S

E

R

V

E

D

POWE

R_DOWN_DELA

Y

RESE

RVE

D

_1

PO

W

E

R_BAC

K

LIG

H

T_OFF_T

O

_P

OWE

R

_DOWN_DELA

Y

31:29

0b

RW

Reserved.

28:16

0b

RW

Programmable value of panel power sequencing delay during 

power up. This provides the time delay for the T3 (T5 for DisplayPort) time sequence. 

The time unit used is the 100us timer.

15:13

0b

RW

Reserved.

12:0

0b

RW

Programmable value of 

panel power sequencing delay during power down. This provides the time delay for the 

Tx (T4 for DisplayPort) time sequence. The time unit used is the 100us timer.