Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

834

Datasheet

31

0b

RW

Setting this bit to the value of one, turns on pipe A. This must be 

done before any planes are enabled on this pipe. Changing it to a zero should only be 

done when all planes that are assigned to this pipe have been disabled. Turning the pipe 

enable bit off disables the timing generator in this pipe. Plane disable occurs after the 

next VBLANK event after the plane is disabled. Synchronization pulses to the display are 

not maintained if the timing generator is disabled. Power consumption will be at it s 

lowest state when disabled. A separate bit controls the DPLL enable for this pipe. Pipe 

timing registers should contain valid values before this bit is enabled.  

0 = Disable  

1 = Enable 

30

0b

RO

This bit indicates the actual state of the pipe. Since there can be some 

delay between disabling the pipe and the pipe actually shutting off, this bit indicates the 

true current state of the pipe. 

0 = Disabled 

1 = Enabled 

AccessType: Read Only

29

0b

RO

This bit indicates the clocks from DSI PLL are locked.  

0 = Unlocked  

1 = Locked  

AccessType: Read only

28:27

0b

RW

(TEST MODE) Used to delay the frame start signal that is sent 

to the display planes. Normal operation uses the default 00 value and test modes can 

use the delayed frame start to shorten the test time. Care must be taken to insure that 

there are enough lines during VBLANK to support this setting. 

00 = Frame Start occurs on the first HBLANK after the start of VBLANK 

01 = Frame Start occurs on the second HBLANK after the start of VBLANK 

10 = Frame Start occurs on the third HBLANK after the start of VBLANK 

11 = Frame Start occurs on the forth HBLANK after the start of VBLANK

26

0b

RW

[DevVLVP] Setting this bit to 1 indicates the 

DisplayPort will output audio only. 

0 = DisplayPort will output Video or Video and Audio 

1 = DisplayPort will output Audio only

25

0b

RW

: (TEST MODE)0 = Normal Operation 

1 = Color information is ignored and border color is substituted during active region

24

0b

RW

This bit selects which mode the pipe gamma 

correction logic works in. In the palette mode, it behaves as a 3X256x8 RAM lookup. 

VGA and indexed mode operation should use the palette in 8-bit mode. In the 10-bit 

gamma mode, it will act as a piecewise linear interpolation. Other gamma units such as 

in the overlay or sprite are unaffected by this bit. 

0 = 8-bit Palette Mode 

1 = 10-bit Gamma Mode

23:21

0b

RW

These bits are used for software control of interlaced behavior. 

They are updated immediately if the pipe is off, or in the vertical blank after 

programming if pipe is enabled. 

0xx = Progressive 

100 = Interlaced embedded panel using programmable vertical sync shift. (2x) 

101 = Interlaced using vertical sync shift. Backup option to 110 setting. (2x) 

110 = Interlaced with VSYNC/HSYNC Field Indication using legacy vertical sync shift. 

Used for SDVO. 

111 = Interlaced with Field 0 Only using legacy vertical sync shift. Not used 

Note: VGA display modes, sDVO line stall, and Panel fitting do not work while in 

interlaced modes 

Setting the Interlaced embedded panel mode causes hardware to automatically modify 

the output to match the specifications of panels that support interlaced mode.

20

0b

RW

0 = Normal 

Operation, display controller generate timing and refresh display panel at refresh rate  

1 = Display self-refresh mode. Display controller update frame buffer in display module 

on demand only