Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Power Management
Intel
®
 Atom™ Processor E3800 Product Family
86
Datasheet
6.2.3
Processor States
6.2.4
Integrated Graphics Display States
G0/S0/Cx
Cx break events which include: CPU 
snoop, MSI, Legacy Interrupt, AONT 
timer
G0/S0/C0
Power Button Override
G2/S5
System Power Failure
G3
G1/S3,G1/S4
Any Enabled Wake Event
G0/S0/C0
Power button Override
G2/S5
Resume Well Power Failure
G3
G2/S5
Any Enabled Wake Event
G0/S0/C0
Resume Well Power Failure
G3
G3
Power Returns
Option to go to S0/C0 (reboot) or G2/S5 
(stay off until power button pressed or 
other enabled wake event) or G1/S4 (if 
system state was S4 prior to the power 
failure). Some wake events are 
preserved through a power failure.
Table 51. Processor Core/ States Support 
State
Description
C0
Active mode, processor executing code
C1
AutoHALT state
C6
Deep Power Down. Prior to entering the Deep Power Down 
Technology (code named C6) State, The core process will flush its 
cache and save its core context to a special on die SRAM on a 
different power plane. Once Deep Power Down Technology (code 
named C6) sequence has completed. The core processor’s voltage 
is completely shut off.
Table 52. SoC Graphics Adapter State Control 
State
Description
D0
Full on, Display active
D3
Power off display
Table 50. ACPI PM State Transition Rules (Sheet 2 of 2)
Present 
State
Transition Trigger
Next State