Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

888

Datasheet

Display A Stride Register

Default: 00000000h

Sprite Color Key Value Register

31:0

0b

RW

This register provides the panning offset into the display A 

plane. This value is added to the surface address to get the graphics address of the first 

pixel to be displayed. This offset must be at least pixel aligned. This offset is the 

difference between the address of the upper left pixel to be displayed and the display 

surface address. When performing 180 rotation, this offset must be the difference 

between the last pixel of the last line of the display data in its unrotated orientation and 

the display surface address.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D

ISP

LA

Y_A_ST

RIDE

R

SVD0

31:6

0b

RW

This is the stride for display A in bytes. When using linear 

memory, this must be 64 byte aligned. When using tiled memory, this must be 512 byte 

aligned. This value is used to determine the line to line increment for the display. This 

register is updated either through a command packet passed through the command 

stream or writes to this register. When it is desired to update both this and the start 

register, the stride register must be written first because the write to the start register is 

the trigger that causes the update of both registers on the next VBLANK event. When 

using tiled memory, the actual memory buffer stride is limited to a maximum of 16K 

bytes. 

[DevBW, DevCL, DevCDV] The display stride must be power of 2 when doing Asynch 

Flips. 

[DevBW, DevCL, DevCDV] The display stride must be 8KB or greater when doing Asynch 

Flips together with 180 rotation. 

The value in this register is updated through the command streamer during a 

synchronous flip.

5:0

0b

RO

Reserved