Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

912

Datasheet

Default: 00000000h

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P

IPE_B_E

NABLE

PIPE

_ST

A

TE

RE

SE

RVED

FRAME_S

TAR

T

_

DELA

Y

DISPLA

Y_POR

T

_A

UDIO_ONL

Y_MODE

FORCE

_

B

O

RDER

PIPE_B_GAMMA_UNIT_MODE

INTERLAC

ED_MODE

MI

PI_DISP

LA

Y

_SELF

_

RE

FRESH_MODE

_FOR_MIPI_

B

DISPLA

Y_OV

ERLA

Y

_

PLA

N

ES_OF

F

C

U

RSOR

_P

LA

NES_OF

F

R

E

FR

ES

H_

RA

T

E

_

C

X

S

R_

M

O

D

E

_

A

S

S

O

C

IA

T

ION

COL

O

R_C

O

RRECTION_MA

TRIX

_

E

NABLE_ON_P

IPE_

B

DISPLA

YPO

R

T_POWER_MO

DE_SWIT

C

H_DEV

V

LV

P

CO

LO

R_RANGE_S

E

LE

C

T

S3D_SP

RITE

_ORDER

S

3

D_SPRITE_INTE

R

LEA

V

ING_FORMA

T

RESE

RVE

D

_1

B

ITS_PER_COL

OR

D

IT

H

ER

ING

_

ENA

B

LE

DITH

ERING_TYPE

DDA_RE

S

E

T

_TES

T_MODE

RESE

RVE

D

_2

31

0b

RW

Setting this bit to the value of one, turns on pipe B. This must be 

done before any planes are enabled on this pipe. Changing it to a zero should only be 

done when all planes that are assigned to this pipe have been disabled. Turning the pipe 

enable bit off disables the timing generator in this pipe. Plane disable occurs after the 

next VBLANK event after the plane is disabled. Synchronization pulses to the display are 

not maintained if the timing generator is disabled. Power consumption will be at its 

lowest state when disabled. A separate bit controls the DPLL enable for this pipe. Pipe 

timing registers should contain valid values before this bit is enabled. 

Disabling the Pipe and changing the timing registers and re-enabling the pipe before the 

next VBLANK will cause the mode change to occur at the end of the current frame. This 

requires no wait on the software s part. On the other hand, if this is the disabling of the 

pipe, that does require a software wait for VBLANK to occur. 

Synchronization pulses to the display are not maintained if the timing generator is 

disabled. Power consumption is at it s lowest state. 

1 = Enable 

0 = Disable

30

0b

RO

This bit indicates the actual state of the pipe. Since there can be some 

delay between disabling the pipe and the pipe actually shutting off, this bit indicates the 

true current state of the pipe. 

0 = Disabled 

1 = Enabled 

AccessType: Read Only

29

0b

RW

Write as zero.