Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

921

Pipe B Frame Counter

Default: 00000000h

Pipe B Flip Counter

1

0b

RW/1C

This status bit will be set on a 

VBLANK event, when the frame start occurs. The display registers are updated at the 

start of vertical blank, but the new register data is not utilized by the display pipeline 

until the point in the vertical blank period when the frame start occurs, which is the 

event that triggers this bit. To use this bit in a polling manner, clear the bit by writing a 

one to it followed by the polling loop waiting for it to become set. 

0 = Pipe B Framestart Status has not occurred 

1 = Pipe B Framestart Status has occurred  

AccessType: One to Clear

0

0b

RW/1C

0 = Pipe B Horizontal Blank has not 

occurred 

1 = Pipe B Horizontal Blank has occurred  

AccessType: One to Clear

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIPE

_B_FRA

ME_

C

O

U

NT

31:0

0b

RO

Provides read back of the display pipe frame counter. This 

counter increments on every start of vertical blank and rolls over back to 0 after 2^32 

frames

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h