Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
930
Datasheet
14.11.256 DSPBSURF—Offset 7119Ch
Display B Surface Address Register
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
0b
RW
RESERVED:
reserved
23:16
0b
RW
RED_MASK_VALUE:
Specifies the color key mask for the sprite red/Cr channel.
15:8
0b
RW
GREEN_MASK_VALUE:
Specifies the color key mask for the sprite green/Y channel.
7:0
0b
RW
BLUE_MASK_VALUE:
Specifies the color key mask for the sprite blue/Cb channel.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISP
LA
Y_B_SU
RF
AC
E_BA
S
E
_ADD
RES
S
RES
E
RVE
D
_MBZ
FLIP_
S
OURCE
D
E
CRY
PT
ION_R
E
Q
UE
ST
RES
E
RV
ED_MBZ_1
Bit
Range
Default &
Access
Field Name (ID): Description
31:12
0b
RW
DISPLAY_B_SURFACE_BASE_ADDRESS:
This address specifies the surface base
address. When the surface is tiled, panning is specified using (x, y) offsets in the
DSPBTILEOFF register. When the surface is in linear memory, panning is specified using
a linear offset in the DSPBLINOFF register.
This address must be 4K aligned. When performing asynchronous flips and the display
surface is in tiled memory, this address must be 256K aligned. This register can be
written directly through software or by command packets in the command stream. It
represents an offset from the graphics memory aperture base and is mapped to physical
pages through the global GTT.
[DevBW] and [DevCL]: This address must be 128K aligned for linear memory.
11:4
0b
RW
RESERVED_MBZ:
Reserved.