Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
932
Datasheet
14.11.258 DSPBSURFLIVE—Offset 711ACh
Display B Live Surface Base Address Register [DevCTG-B, DevCDV]
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SE
RVED
PL
ANE_ST
A
R
T_Y
_
PO
SITIO
N
RESE
RVED
_1
PL
ANE_S
TAR
T
_
X_PO
SITIO
N
Bit
Range
Default &
Access
Field Name (ID): Description
31:28
0b
RW
RESERVED:
Write as zero
27:16
0b
RW
PLANE_START_Y_POSITION:
These 12 bits specify the vertical position in lines of the
beginning of the active display plane relative to the display surface. When performing
180 rotation, this field specifies the vertical position of the lower right corner relative to
the start of the active display plane in the unrotated orientation.
15:12
0b
RW
RESERVED_1:
Write as zero
11:0
0b
RW
PLANE_START_X_POSITION:
These 12 bits specify the horizontal offset in pixels of
the beginning of the active display plane relative to the display surface. When
performing 180 rotation, this field specifies the horizontal position of the lower right
corner relative to the start of the active display plane in the unrotated orientation.
[DevBW, DevCL, DevCDV] When display stride is 16KB and doing Asynch Flips, do not
program the offset to give pans of 7680 to 8191 bytes.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h