Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Power Up and Reset Sequence
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
99
fetch the descriptor region and soft straps data from the PCU located SPI interface,
followed by the SoC de-asserting PMC_SUS_STAT#.
followed by the SoC de-asserting PMC_SUS_STAT#.
10. The SoC de-asserts PMC_PLTRST# after PMC_SUS_STAT# is stable. The
PMC_PLTRST# is the main platform reset to other components.
11. The SoC will begin fetching data from the PCU-located SPI interface and proceed to
finish initialization and start code execution (BIOS).
Note:
There is no hard time requirement for transitions for the Always on/SUS rails (V1.0A,
V1.2A, V1.8A, V3.3A). A 10us to 2000us delay is required for two adjacent rails of them
to avoid inrush current which may be caused by multiple loads turning on
simultaneously or fast charging of VR output decoupling.
V1.2A, V1.8A, V3.3A). A 10us to 2000us delay is required for two adjacent rails of them
to avoid inrush current which may be caused by multiple loads turning on
simultaneously or fast charging of VR output decoupling.