Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1988
Datasheet
17.8.33
Port-Command (PxCMD1)—Offset 198h
Access Method
Default: 00000004h
2
0h
RW
DMA Setup FIS Interrupt Enable (DSE):
When set, GHC.IE is set, and P0IS.DSS is
set, the HBA shall generate an interrupt.
1
0h
RW
PIO Setup FIS Interrupt Enable (PSE):
When set, GHC.IE is set, and P0IS.PSS is
set, the HBA shall generate an interrupt.
0
0h
RW
Device to Host Register FIS Interrupt Enable (DHRE):
When set, GHC.IE is set,
and P0IS.DHRS is set, the HBA shall generate an interrupt.
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
PxCMD1:
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
IC
C
AS
P
AL
PE
DLA
E
ATA
PI
AP
ST
E
FBS
C
P
ES
P
CPD
MPSP
HPC
P
PMA
RS
VD0
CR
FR
MPS
S
CCS
RS
VD1
PS
P
AP
S
E
FRE
CL
O
PO
D
SU
D
ST
Bit
Range
Default &
Access
Description
31:28
0h
RW
Interface Communication Control (ICC):
This is a four bit field which can be used to
control reset and power states of the interface. If the Link layer is currently in the
L_IDLE state, writes to this field shall cause the HBA to initiate a transition to the
interface power management state requested. If the Link layer is not currently in the
L_IDLE state, writes to this field shall have no effect. Fh -9h Reserved. 8h DEVSLP: This
shall cause the HBA to assert the DEVSLP signal associated with the port; the HBA shall
ignore the DEVSLP Idle Timeout value specified by PxDEVSLP.DITO. Software shall only
request DEVSLP when the interface is in an idle state (i.e. PxCI is cleared to 0h and
PxSACT is cleared to 0h); if the interface is not idle at the time the register is written,
then the HBA takes no action and the interface remains in its current state. If
PxCAP2.DESO is set to '1' and PxSSTS.IPM is not set to '6h', then the HBA takes no
action and the interface remains in its current state. Additionally, the HBA shall not
assert the DEVSLP signal until PHYRDY has been achieved (after a previous de-
assertion). 7h Reserved 6h Slumber: This shall cause the HBA to request a transition of
the interface to the Slumber state. The SATA device may reject the request and the
interface shall remain in its current state. 5h-3h Reserved. 2h Partial: This shall cause
the HBA to request a transition of the interface to the Partial state. The SATA device may
reject the request and the interface shall remain in its current state. 1h Active: This
shall cause the HBA to request a transition of the interface into the active state. If the
requested transition is from the DEVSLP state, then the HBA shall wait until
PxDEVSLP.DMAT has expired before de-asserting the DEVSLP signal. 0h No-Op / Idle:
When software reads this value, it indicates the HBA is ready to accept a new interface
control command, although the transition to the previously selected state may not yet
have occurred. When system software writes a non-reserved value other than No-Op
(0h), the HBA shall perform the action and update this field back to Idle (0h). If
software writes to this field to change the state to a state the link is already in (i.e.
interface is in the active state and a request is made to go to the active state), the HBA
shall take no action and return this field to Idle. If the interface is in a low power state
and the software wants to transition to a different low power state, software must first
bring the link to active and then initiate the transition to the desired low power state
(with the exception of DEVSLP). The transition to DEVSLP may occur from any other
state if CAP2.DESO is cleared to '0'. If CAP2.DESO is set to '1', then DEVSLP may only
be transitioned to if the link is in Slumber.