Nxp Semiconductors LPC2917 User Manual
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LPC2917_19_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 1.01 — 15 November 2007
10 of 68
NXP Semiconductors
LPC2917/19
ARM9 microcontroller with CAN and LIN
7.
Functional description
7.1 Reset, debug, test and power description
7.1.1 Reset and power-up behavior
The LPC2917/19 contains external reset input and internal power-up reset circuits. This
ensures that a reset is extended internally until the oscillators and flash have reached a
stable state. See
ensures that a reset is extended internally until the oscillators and flash have reached a
stable state. See
for trip levels of the internal power-up reset circuit
1
. See
for characteristics of the several start-up and initialization times.
shows
the reset pin.
At activation of the RSTN pin the JTAGSEL pin is sensed as logic LOW. If this is the case
the LPC2917/19 is assumed to be connected to debug hardware, and internal circuits
re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the
Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when
running at LP_OSC speed is too low for the external debugging environment.
the LPC2917/19 is assumed to be connected to debug hardware, and internal circuits
re-program the source for the BASE_SYS_CLK to be the crystal oscillator instead of the
Low-Power Ring Oscillator (LP_OSC). This is required because the clock rate when
running at LP_OSC speed is too low for the external debugging environment.
7.1.2 Reset strategy
The LPC2917/19 contains a central module, the Reset Generator Unit (RGU) in the
Power, Clock and Reset Control Subsystem (PCRSS), which controls all internal reset
signals towards the peripheral modules. The RGU provides individual reset control as well
as the monitoring functions needed for tracing a reset back to source.
Power, Clock and Reset Control Subsystem (PCRSS), which controls all internal reset
signals towards the peripheral modules. The RGU provides individual reset control as well
as the monitoring functions needed for tracing a reset back to source.
P0.18
132
GPIO 0, pin 18
ADC2 IN2
PWM2 MAT0
EXTBUS A14
P0.19
133
GPIO 0, pin 19
ADC2 IN3
PWM2 MAT1
EXTBUS A15
P3.4
134
GPIO 3, pin 4
TIMER3 MAT2
PWM2 MAT4
CAN1 TxD
P3.5
135
GPIO 3, pin 5
TIMER3 MAT3
PWM2 MAT5
CAN1 RxD
P2.18
136
GPIO 2, pin 18
-
PWM1 CAP1
EXTBUS D16
P2.19
137
GPIO 2, pin 19
-
PWM1 CAP2
EXTBUS D17
P0.20
138
GPIO 0, pin 20
ADC2 IN4
PWM2 MAT2
EXTBUS A16
P0.21
139
GPIO 0, pin 21
ADC2 IN5
PWM2 MAT3
EXTBUS A17
P0.22
140
GPIO 0, pin 22
ADC2 IN6
PWM2 MAT4
EXTBUS A18
V
SS(IO)
141
ground for I/O
P0.23
142
GPIO 0, pin 23
ADC2 IN7
PWM2 MAT5
EXTBUS A19
P2.20
143
GPIO 2, pin 20
-
PWM2 CAP0
EXTBUS D18
TDI
144
IEEE 1149.1 data in, pulled up internally.
Table 3.
LQFP144 pin assignment
…continued
Symbol
Pin
Description
Function 0 (default)
Function 1
Function 2
Function 3
1.
Only for 1.8 V power sources
Table 4.
Reset pin
Symbol
Direction
Description
RSTN
in
external reset input, active LOW; pulled up internally