User ManualTable of Contents1. General description12. Features13. Applications24. Ordering information25. Block diagram36. Pinning information46.1 Pinning46.2 Pin description57. Functional description67.1 General67.2 Internal oscillator67.3 Registers67.3.1 Direct registers87.3.1.1 The Status register, I2CSTA (A1=0, A0=0)87.3.1.2 The Indirect Pointer register, INDPTR (A1=0, A0=0)87.3.1.3 The I2C-bus Data register, I2CDAT (A1=0, A0=1)87.3.1.4 The Control register, I2CCON (A1=1, A0=1)97.3.1.5 The indirect data field access register, INDIRECT (A1 = 1, A0=0)117.3.2 Indirect registers127.3.2.1 The Byte Count register, I2CCOUNT (indirect address 00h)127.3.2.2 The Own Address register, I2CADR (indirect address 01h)127.3.2.3 The Clock Rate registers, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h)137.3.2.4 The Time-out register, I2CTO (indirect address 04h)147.3.2.5 The Parallel Software Reset register, I2CPRESET (indirect address 05h)147.3.2.6 The I2C-bus mode register, I2CMODE (indirect address 06h)158. PCA9665 modes168.1 Configuration modes168.1.1 Byte mode168.1.2 Buffered mode168.2 Operating modes168.3 Byte mode178.3.1 Master Transmitter Byte mode178.3.2 Master Receiver Byte mode228.3.3 Slave Receiver Byte mode258.3.4 Slave Transmitter Byte mode298.4 Buffered mode318.4.1 Master Transmitter Buffered mode318.4.2 Master Receiver Buffered mode368.4.3 Slave Receiver Buffered mode408.4.4 Slave Transmitter Buffered mode458.5 Buffered mode examples488.5.1 Buffered Master Transmitter mode of operation488.5.2 Buffered Master Receiver mode of operation488.5.3 Buffered Slave Transmitter mode498.5.4 Buffered Slave Receiver mode508.5.5 Example: Read 128 bytes in two 64-byte sequences of an EEPROM (I2C-busaddress=A0h for wr...508.6 I2CCOUNT register518.7 Acknowledge management (I2C-bus addresses and data) in Byte and Buffered modes538.8 Miscellaneous states578.8.1 I2CSTA=F8h578.8.2 I2CSTA=00h578.8.3 I2CSTA=70h578.8.4 I2CSTA=78h588.9 Some special cases588.9.1 Simultaneous repeated START conditions from two masters588.9.2 Data transfer after loss of arbitration588.9.3 Forced access to the I2C-bus588.9.4 I2C-bus obstructed by a LOW level on SCL or SDA598.9.5 Bus error608.10 Power-on reset608.11 Reset618.12 I2C-bus timing diagrams, Unbuffered mode618.13 I2C-bus timing diagrams, Buffered mode639. Characteristics of the I2C-bus659.1 Bit transfer659.1.1 START and STOP conditions659.2 System configuration659.3 Acknowledge6610. Application design-in information6710.1 Specific applications6710.2 Add I2C-bus port6710.3 Add additional I2C-bus ports6810.4 Convert 8bits of parallel data into I2C-bus serial data stream6811. Limiting values6912. Static characteristics7013. Dynamic characteristics7114. Test information7815. Package outline7916. Handling information8317. Soldering8317.1 Introduction8317.2 Through-hole mount packages8317.2.1 Soldering by dipping or by solder wave8317.2.2 Manual soldering8317.3 Surface mount packages8317.3.1 Reflow soldering8317.3.2 Wave soldering8517.3.3 Manual soldering8517.4 Package related soldering information8518. Abbreviations8719. Revision history8720. Legal information8920.1 Data sheet status8920.2 Definitions8920.3 Disclaimers8920.4 Trademarks8921. Contact information8922. Contents90Size: 431 KBPages: 91Language: EnglishOpen manual