SMSC LAN9420i Manual De Usuario

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

SMSC LAN9420/LAN9420i

149

Revision 1.22 (09-25-08)

Configuration and read back of the CONFIG CSR is accomplished by the Host processor via the PCI
bus. These registers assume their default value on assertion of a chip-level reset or when the device
power state transitions from D3 to D0. See 

 for details. 

Registers in offsets 00h - 03Fh are standard PCI header registers, as described in the PCI Local Bus
Specification Revision 3.0. Please refer to the specification for further details. 

Register 78h is a PCIB specific extension related to power management.

The following is the register map for the PCI Configuration Space CSR (CONFIG CSR):

00h – 3Fh

-

Standard PCI Header Registers (See 

for details).

40h – 74h

78h

PCI_PMC

7Ch

PCI_PMCSR