SMSC LAN9420i Manual De Usuario
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
151
Revision 1.22 (09-25-08)
DATASHEET
4.6.1
PCI Power Management Capabilities Register (PCI_PMC)
This register implements the standard capability structure used to define power management features
in a PCI device. The capabilities structure is documented in the PCI Bus Power Management Interface
Specification Revision 1.1. The host uses this register check supported power states and features.
in a PCI device. The capabilities structure is documented in the PCI Bus Power Management Interface
Specification Revision 1.1. The host uses this register check supported power states and features.
Note: The format of this register is equivalent to offsets 3:0 of the Power Management Register Block
Definition as described in the PCI Bus Power Management Interface Specification Revision 1.1.
Offset:
78h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31
PME Support from D3
COLD
(PME_IN_D3C)
When this bit is set, LAN9420/LAN9420i is capable asserting nPME from the
D3
D3
COLD
state. When this bit is cleared, the device will not assert nPME from
the D3
COLD
state.
This bit reflects the setting of the VAUXDET input pin.
RO
30
PME Support from D3
HOT
(PME_IN_D3H)
This bit is set indicating that LAN9420/LAN9420i is capable asserting nPME
from the D3
from the D3
HOT
state.
RO
1b
29
PME Support from D2 (PME_IN_D2)
This bit is cleared since LAN9420/LAN9420i does not support the D2 power
management state.
This bit is cleared since LAN9420/LAN9420i does not support the D2 power
management state.
RO
0b
28
PME Support from D1 (PME_IN_D1)
This bit is cleared since LAN9420/LAN9420i does not support the D1 power
management state.
This bit is cleared since LAN9420/LAN9420i does not support the D1 power
management state.
RO
0b
27
PME Support from D0 (PME_IN_D0)
This bit is set indicating that LAN9420/LAN9420i is capable asserting nPME
from the D0 state.
This bit is set indicating that LAN9420/LAN9420i is capable asserting nPME
from the D0 state.
RO
1b
26
D2 Power State Support (D2_SUP)
This bit is cleared since LAN9420/LAN9420i does not support the D2 power
management state.
This bit is cleared since LAN9420/LAN9420i does not support the D2 power
management state.
RO
0b
25
D1 Power State Support (D1_SUP)
This bit is cleared since LAN9420/LAN9420i does not support the D1 power
management state.
This bit is cleared since LAN9420/LAN9420i does not support the D1 power
management state.
RO
0b
24:22
3.3Vaux Power Supply Current Draw (AUX_CURRENT)
This field indicates the auxiliary power requirements for the
LAN9420/LAN9420i device. This field is dependant on the state of the
VAUXDET input pin.
This field indicates the auxiliary power requirements for the
LAN9420/LAN9420i device. This field is dependant on the state of the
VAUXDET input pin.
When VAUXDET is cleared, this field is cleared to 000b to indicate that there
is no current draw from the 3.3Vaux power supply. When VAUXDET is set,
this field is set to a value of 110b to indicate a current draw of 320mA from
the 3.3Vaux power supply.
is no current draw from the 3.3Vaux power supply. When VAUXDET is set,
this field is set to a value of 110b to indicate a current draw of 320mA from
the 3.3Vaux power supply.
RO
21
Device Specific Initialization (DSI)
This bit returns zero, indicating that there are no device specific initialization
requirements.
This bit returns zero, indicating that there are no device specific initialization
requirements.
RO
0b
20
RESERVED
RO
0b
19
PME Clock (CLK4PME)
This bit is cleared to indicate that LAN9420/LAN9420i does not require the
presence of PCICLK in order to assert nPME.
This bit is cleared to indicate that LAN9420/LAN9420i does not require the
presence of PCICLK in order to assert nPME.
RO
0b