Texas Instruments TMS320C64x DSP Benutzerhandbuch
Reset Operation
Video Port
2-4
SPRU629
Once the port is configured and the VCEN bit is set, the setting of other
VCxCTL bits (except VCEN, RSTCH, and BLKCAP) is prohibited and the
capture counters begin counting. When BLKCAP is cleared, data capture and
event generation may begin.
VCxCTL bits (except VCEN, RSTCH, and BLKCAP) is prohibited and the
capture counters begin counting. When BLKCAP is cleared, data capture and
event generation may begin.
2.1.5
Display Channel Reset
A software reset may be performed on the display channel by setting the
RSTCH bit in VDCTL. This reset requires that the channel VCLKIN be trans-
itioning. On display channel reset:
RSTCH bit in VDCTL. This reset requires that the channel VCLKIN be trans-
itioning. On display channel reset:
-
No new DMA events are generated.
-
Peripheral bus accesses are acknowledged (WREADY returned) to prevent
DMA lock-up. (Write data may be written into the FIFO or discarded.)
DMA lock-up. (Write data may be written into the FIFO or discarded.)
-
Channel display registers are set to their default values.
-
Channel display FIFO is flushed (pointers reset).
-
The VDEN bit in VDCTL is cleared to 0.
-
The RSTCH bit self-clears to 0 after completion of the above.
Once the port is configured and the VDEN bit is set, the setting of other VDCTL
bits (except VDEN, RSTCH, and BLKDIS) is prohibited and the display counters
begin counting. Data outputs are driven (with default value, blanking, and
control codes as appropriate and any control outputs are driven). When the
BLKDIS bit is cleared, event generation may begin and FIFO data displayed.
bits (except VDEN, RSTCH, and BLKDIS) is prohibited and the display counters
begin counting. Data outputs are driven (with default value, blanking, and
control codes as appropriate and any control outputs are driven). When the
BLKDIS bit is cleared, event generation may begin and FIFO data displayed.