Texas Instruments TMS320C64x DSP Benutzerhandbuch

2-5

The video port can generate an interrupt to the DSP core after any of the follow-
ing events occur:

-

Capture complete (CCMPx) bit is set.

-

Capture overrun (COVRx) bit is set.

-

Synchronization byte error (SERRx) bit is set.

-

Vertical interrupt (VINTxn) bit is set.

-

Short field detect (SFDx) bit is set.

-

Long field detect (LFDx) bit is set.

-

STC absolute time (STC) bit is set.

-

STC tick counter expired (TICK) bit is set.

-

Display complete (DCMP) bit is set.

-

Display underrun (DUND) bit is set.

-

Display complete not acknowledged (DCNA) bit is set.

-

GPIO interrupt (GPIO) bit is set.

The interrupt signal is a pulse only and does not hold state. The interrupt pulse
is generated only when the number of set flags in VPIS transitions from none
to one or more. Another interrupt pulse is not generated by setting additional
flag bits.

Interrupts can be masked via the video port interrupt enable register (VPIE)
using individual interrupt enables and the VIE global enable bit. The interrupts
are cleared in the video port interrupt status register (VPIS) using the individual
status bits. Writing a 1 to the appropriate bit clears the interrupt. The clearing
of an interrupt flag reenables the generation of another interrupt pulse, if other
flags are still set. In other words, pulse generation is reenabled by writing a 1
to any set bit of VPIS.

Upon receiving an interrupt you should:

1) Read VPIS.

2) Perform the service routine for whatever bits are set.

3) Clear appropriate bits by writing a 1 to their VPIS locations.

4) Upon return from the ISR, if VPIS bits have been (or remain) set, then

another interrupt will occur.