Texas Instruments TMS320C64x DSP Benutzerhandbuch

2-6

The video port uses up to three DMA events per channel for a total of six
possible events. Each DMA event uses a dedicated event output. The outputs
are:

-

VPYEVTA

-

VPCbEVTA

-

VPCrEVTA

-

VPYEVTB

-

VPCbEVTB

-

VPCrEVTB

Capture DMA events are generated based on the state of the capture FIFO(s).
If no DMA event is currently pending and the FIFO crosses the value specified
by VCTHRLDn, a DMA event is generated. Once an event has been
requested, another DMA event may not be generated until the servicing of the
outstanding event has begun (as indicated by the first read of the FIFO by the
DMA event service). If the capture FIFO level exceeds 2

×

 the VCTHRLDn

value before the requested DMA event completes, then another DMA event
may be generated. Thus, up to one DMA event may be outstanding.

An outgoing data counter counts data read by the DMA. This counter is loaded
with the VCTHRLDn value whenever a new DMA service begins. The counter
then counts down for each double-word read from the FIFO by the DMA. The
DMA is complete when the counter reaches zero. Figure 2–1 shows the
capture DMA event generation.

For BT.656 and Y/C modes, there are three FIFOs, one for each of the Y, Cb,
and Cr color components. Each FIFO generates its own DMA event; therefore,
the DMA event state and FIFO thresholds for each FIFO are tracked indepen-
dently. The Cb and Cr FIFOs use a threshold value of

½

 (VCTHRLDn + VCTHRLDn mod 2).