Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
Receive FIFO Request Raw Interrupt Status
Description
Value
No interrupt
0
The trigger value for the FIFO has been reached and a RX FIFO
Request interrupt is pending.
Request interrupt is pending.
1
This bit is cleared by writing a 1 to the
RXIC
bit in the I2CSICR register.
0
RO
RXRIS
6
Transmit Request Raw Interrupt Status
Description
Value
No interrupt
0
The trigger value for the FIFO has been reached and a TX FIFO
Request interrupt is pending.
Request interrupt is pending.
1
This bit is cleared by writing a 1 to the
TXIC
bit in the I2CSICR register.
0
RO
TXRIS
5
Transmit DMA Raw Interrupt Status
Description
Value
No interrupt.
0
A transmit DMA complete interrupt is pending.
1
This bit is cleared by writing a 1 to the
DMATXIC
bit in the I2CSICR
register.
0
RO
DMATXRIS
4
Receive DMA Raw Interrupt Status
Description
Value
No interrupt.
0
A receive DMA complete interrupt is pending.
1
This bit is cleared by writing a 1 to the
DMARXIC
bit in the I2CSICR
register.
0
RO
DMARXRIS
3
Stop Condition Raw Interrupt Status
Description
Value
No interrupt.
0
A STOP condition interrupt is pending.
1
This bit is cleared by writing a 1 to the
STOPIC
bit in the I2CSICR
register.
0
RO
STOPRIS
2
Start Condition Raw Interrupt Status
Description
Value
No interrupt.
0
A START condition interrupt is pending.
1
This bit is cleared by writing a 1 to the
STARTIC
bit in the I2CSICR
register.
0
RO
STARTRIS
1
December 13, 2013
1488
Texas Instruments-Advance Information
Inter-Integrated Circuit (I
2
C) Interface