Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Figure 24-4. RMII Clock Structure
Ethernet MAC
External PHY
MOSC
PTPCEN
RX+
RX-
TX+
TX-
Gated SYSCLK
PTP_REFCLK
MAC Control /
Status Registers
EMACCC
Tiva Cortex-M4
Microcontroller
Microcontroller
EN0REF_CLK (50 MHz Clock)
EN0RXDV
EN0TXEN
EN0MDIO
EN0MDC
EN0INTRN
EN0RXD1
EN0RXD0
EN0TXD1
EN0TXD0
Clock
Source
Needed
24.3.2
MII/RMII Interface Signals
The MAC Module has the capability of providing an MII or RMII interface depending on the interface
selected in the Ethernet MAC Peripheral Configuration (EMACPC) register, at offset 0xFC4.
Except for
selected in the Ethernet MAC Peripheral Configuration (EMACPC) register, at offset 0xFC4.
Except for
EN0REF_CLK
, the signals used for RMII mode are a subset of the MII interface signals.
Thus, Table 24-2 on page 1591 details the MII signals that are used in RMII mode and the RMII function
to which they correspond. In addition, the GPIO pin they are muxed with is listed.
to which they correspond. In addition, the GPIO pin they are muxed with is listed.
Table 24-2. MII and RMII Interface Signals
GPIO
RMII Standard Name and Function
RMII
MII Signal
PM4
REF_CLK: Synchronous clock reference for
receive, transmit and control
receive, transmit and control
EN0REF_CLK
N/A
PG2
N/A
Not Used
EN0TXCK
PK7
N/A
Not Used
EN0TD3
PK6
N/A
Not Used
EN0TXD2
PG5/PS5
TXD1: Transmit Data 1
EN0TXD1
EN0TXD1
PG4/PS4
TXD0: Transmit Data 0
EN0TXD0
EN0TXD0
PG3/PR7
TEX_EN: Transmit Enable
EN0TXEN
EN0TXEN
PN6
N/A
Not Used
EN0TXER
PA6
N/A
Not Used
EN0RXCK
PK4
N/A
Not Used
EN0RXD3
PK5
N/A
Not Used
EN0RXD2
PQ6/PT1
RXD1: Receive Data 1
EN0RXD1
EN0RXD1
1591
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller