Texas Instruments CC2650DK Benutzerhandbuch
µDMA Registers
12.5.1.7 SETBURST Register (Offset = 18h) [reset = X]
SETBURST is shown in
and described in
.
Channel Set UseBurst
Figure 12-13. SETBURST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CHNLS
R/W-X
Table 12-14. SETBURST Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
CHNLS
R/W
X
Returns the useburst status, or disables individual channels from
generating single uDMA requests. The value R is the arbitration rate
and stored in the controller data structure. Read as: Bit [Ch] = 0:
uDMA channel Ch responds to both burst and single requests on
channel C. The controller performs 2^R, or single, bus transfers. Bit
[Ch] = 1: uDMA channel Ch does not respond to single transfer
requests. The controller only responds to burst transfer requests and
performs 2^R transfers. Write as: Bit [Ch] = 0: No effect. Use the
CLEARBURST.CHNLS to set bit [Ch] to 0. Bit [Ch] = 1: Disables
single transfer requests on channel Ch. The controller performs 2^R
transfers for burst requests. Writing to a bit where a uDMA channel
is not implemented has no effect
generating single uDMA requests. The value R is the arbitration rate
and stored in the controller data structure. Read as: Bit [Ch] = 0:
uDMA channel Ch responds to both burst and single requests on
channel C. The controller performs 2^R, or single, bus transfers. Bit
[Ch] = 1: uDMA channel Ch does not respond to single transfer
requests. The controller only responds to burst transfer requests and
performs 2^R transfers. Write as: Bit [Ch] = 0: No effect. Use the
CLEARBURST.CHNLS to set bit [Ch] to 0. Bit [Ch] = 1: Disables
single transfer requests on channel Ch. The controller performs 2^R
transfers for burst requests. Writing to a bit where a uDMA channel
is not implemented has no effect
1060
Micro Direct Memory Access (µDMA)
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated