Texas Instruments CC2650DK Benutzerhandbuch
µDMA Registers
12.5.1.9 SETREQMASK Register (Offset = 20h) [reset = X]
SETREQMASK is shown in
and described in
Channel Set Request Mask
Figure 12-15. SETREQMASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CHNLS
R/W-X
Table 12-16. SETREQMASK Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
CHNLS
R/W
X
Returns the burst and single request mask status, or disables the
corresponding channel from generating uDMA requests. Read as: Bit
[Ch] = 0: External requests are enabled for channel Ch. Bit [Ch] = 1:
External requests are disabled for channel Ch. Write as: Bit [Ch] = 0:
No effect. Use the CLEARREQMASK.CHNLS to enable uDMA
requests. Bit [Ch] = 1: Disables uDMA burst request channel [C] and
uDMA single request channel [C] input from generating uDMA
requests. Writing to a bit where a uDMA channel is not implemented
has no effect
corresponding channel from generating uDMA requests. Read as: Bit
[Ch] = 0: External requests are enabled for channel Ch. Bit [Ch] = 1:
External requests are disabled for channel Ch. Write as: Bit [Ch] = 0:
No effect. Use the CLEARREQMASK.CHNLS to enable uDMA
requests. Bit [Ch] = 1: Disables uDMA burst request channel [C] and
uDMA single request channel [C] input from generating uDMA
requests. Writing to a bit where a uDMA channel is not implemented
has no effect
1062
Micro Direct Memory Access (µDMA)
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated