Texas Instruments CC2650DK Benutzerhandbuch
µDMA Registers
12.5.1.8 CLEARBURST Register (Offset = 1Ch) [reset = X]
CLEARBURST is shown in
and described in
Channel Clear UseBurst
Figure 12-14. CLEARBURST Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CHNLS
W-X
Table 12-15. CLEARBURST Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
CHNLS
W
X
Set the appropriate bit to enable single transfer requests. Write as:
Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single
transfer requests. Bit [Ch] = 1: Enables single transfer requests on
channel Ch. Writing to a bit where a DMA channel is not
implemented has no effect.
Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single
transfer requests. Bit [Ch] = 1: Enables single transfer requests on
channel Ch. Writing to a bit where a DMA channel is not
implemented has no effect.
1061
SWCU117A – February 2015 – Revised March 2015
Micro Direct Memory Access (µDMA)
Copyright © 2015, Texas Instruments Incorporated